Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5438351 [patent_doc_number] => 20090089990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'METHOD FOR MANUFACTURING SOLID ELECTROLYTIC CAPACITOR' [patent_app_type] => utility [patent_app_number] => 12/244248 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4455 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089990.pdf [firstpage_image] =>[orig_patent_app_number] => 12244248 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/244248
METHOD FOR MANUFACTURING SOLID ELECTROLYTIC CAPACITOR Oct 1, 2008 Abandoned
Array ( [id] => 6375377 [patent_doc_number] => 20100081279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Method for Forming Through-base Wafer Vias in Fabrication of Stacked Devices' [patent_app_type] => utility [patent_app_number] => 12/242002 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11043 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20100081279.pdf [firstpage_image] =>[orig_patent_app_number] => 12242002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242002
Method for Forming Through-base Wafer Vias in Fabrication of Stacked Devices Sep 29, 2008 Abandoned
Array ( [id] => 6375097 [patent_doc_number] => 20100081237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/242111 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6211 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20100081237.pdf [firstpage_image] =>[orig_patent_app_number] => 12242111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242111
Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device Sep 29, 2008 Abandoned
Array ( [id] => 92068 [patent_doc_number] => 07737028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Selective ruthenium deposition on copper materials' [patent_app_type] => utility [patent_app_number] => 12/240822 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737028.pdf [firstpage_image] =>[orig_patent_app_number] => 12240822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240822
Selective ruthenium deposition on copper materials Sep 28, 2008 Issued
Array ( [id] => 5428658 [patent_doc_number] => 20090087968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/237972 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2352 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20090087968.pdf [firstpage_image] =>[orig_patent_app_number] => 12237972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237972
Method for fabricating fine pattern in semiconductor device Sep 24, 2008 Issued
Array ( [id] => 6372317 [patent_doc_number] => 20100075510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Method for Pulsed plasma deposition of titanium dioxide film' [patent_app_type] => utility [patent_app_number] => 12/237902 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2275 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20100075510.pdf [firstpage_image] =>[orig_patent_app_number] => 12237902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237902
Method for Pulsed plasma deposition of titanium dioxide film Sep 24, 2008 Abandoned
Array ( [id] => 1076378 [patent_doc_number] => 07614888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Flip chip package process' [patent_app_type] => utility [patent_app_number] => 12/237052 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 1413 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/614/07614888.pdf [firstpage_image] =>[orig_patent_app_number] => 12237052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237052
Flip chip package process Sep 23, 2008 Issued
Array ( [id] => 5416515 [patent_doc_number] => 20090042402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/236122 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 7669 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20090042402.pdf [firstpage_image] =>[orig_patent_app_number] => 12236122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236122
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Sep 22, 2008 Abandoned
Array ( [id] => 5508680 [patent_doc_number] => 20090081887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Heat treatment method and heat treatment apparatus' [patent_app_type] => utility [patent_app_number] => 12/232751 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20090081887.pdf [firstpage_image] =>[orig_patent_app_number] => 12232751 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/232751
Heat treatment method wherein the substrate holder is composed of two holder constituting bodies that move relative to each other Sep 22, 2008 Issued
Array ( [id] => 5379874 [patent_doc_number] => 20090191713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'METHOD OF FORMING FINE PATTERN USING BLOCK COPOLYMER' [patent_app_type] => utility [patent_app_number] => 12/235361 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8566 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20090191713.pdf [firstpage_image] =>[orig_patent_app_number] => 12235361 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/235361
METHOD OF FORMING FINE PATTERN USING BLOCK COPOLYMER Sep 21, 2008 Abandoned
Array ( [id] => 4533368 [patent_doc_number] => 07888174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Embedded chip package process' [patent_app_type] => utility [patent_app_number] => 12/234702 [patent_app_country] => US [patent_app_date] => 2008-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2778 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888174.pdf [firstpage_image] =>[orig_patent_app_number] => 12234702 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234702
Embedded chip package process Sep 20, 2008 Issued
Array ( [id] => 6371980 [patent_doc_number] => 20100075445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Silicon Microchannel Plate Devices With Smooth Pores And Precise Dimensions' [patent_app_type] => utility [patent_app_number] => 12/234641 [patent_app_country] => US [patent_app_date] => 2008-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5700 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20100075445.pdf [firstpage_image] =>[orig_patent_app_number] => 12234641 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234641
Silicon microchannel plate devices with smooth pores and precise dimensions Sep 19, 2008 Issued
Array ( [id] => 7593276 [patent_doc_number] => 07651924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Method of fabricating semiconductor memory device in which an oxide film fills a trench in a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 12/233052 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5109 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/651/07651924.pdf [firstpage_image] =>[orig_patent_app_number] => 12233052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233052
Method of fabricating semiconductor memory device in which an oxide film fills a trench in a semiconductor substrate Sep 17, 2008 Issued
Array ( [id] => 200141 [patent_doc_number] => 07640072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Substrate processing apparatus, control method for the apparatus, and program for implementing the method' [patent_app_type] => utility [patent_app_number] => 12/125959 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7951 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640072.pdf [firstpage_image] =>[orig_patent_app_number] => 12125959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125959
Substrate processing apparatus, control method for the apparatus, and program for implementing the method May 22, 2008 Issued
Array ( [id] => 4904086 [patent_doc_number] => 20080113499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Semiconductor device with mushroom electrode and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 12/003559 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8189 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20080113499.pdf [firstpage_image] =>[orig_patent_app_number] => 12003559 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/003559
Semiconductor device with mushroom electrode and manufacture method thereof Dec 27, 2007 Issued
Array ( [id] => 6490230 [patent_doc_number] => 20100009550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'METHOD AND APPARATUS FOR MODIFYING INTEGRATED CIRCUIT BY LASER' [patent_app_type] => utility [patent_app_number] => 12/517651 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3375 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009550.pdf [firstpage_image] =>[orig_patent_app_number] => 12517651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/517651
METHOD AND APPARATUS FOR MODIFYING INTEGRATED CIRCUIT BY LASER Dec 6, 2007 Abandoned
Array ( [id] => 5561617 [patent_doc_number] => 20090134469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH DUAL FULLY SILICIDED GATE' [patent_app_type] => utility [patent_app_number] => 11/946776 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 11133 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134469.pdf [firstpage_image] =>[orig_patent_app_number] => 11946776 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946776
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH DUAL FULLY SILICIDED GATE Nov 27, 2007 Abandoned
Array ( [id] => 4782694 [patent_doc_number] => 20080136023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/945736 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8239 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136023.pdf [firstpage_image] =>[orig_patent_app_number] => 11945736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945736
Method for manufacturing semiconductor device and semiconductor device Nov 26, 2007 Issued
Array ( [id] => 4692818 [patent_doc_number] => 20080085589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'FABRICATION OF STRAINED SILICON FILM VIA IMPLANTATION AT ELEVATED SUBSTRATE TEMPERATURES' [patent_app_type] => utility [patent_app_number] => 11/941324 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1440 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085589.pdf [firstpage_image] =>[orig_patent_app_number] => 11941324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941324
FABRICATION OF STRAINED SILICON FILM VIA IMPLANTATION AT ELEVATED SUBSTRATE TEMPERATURES Nov 15, 2007 Abandoned
Array ( [id] => 277905 [patent_doc_number] => 07556979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging' [patent_app_type] => utility [patent_app_number] => 11/932385 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 8737 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/556/07556979.pdf [firstpage_image] =>[orig_patent_app_number] => 11932385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932385
Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging Oct 30, 2007 Issued
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