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Scott Rand

Examiner (ID: 15889)

Most Active Art Unit
1209
Art Unit(s)
1209
Total Applications
286
Issued Applications
196
Pending Applications
9
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20635799 [patent_doc_number] => 12596673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Systems and methods for implementing directional operand broadcast and multiply-accumulate execution using a configurable patch mesh in a multi-core processing array of an integrated circuit [patent_app_type] => utility [patent_app_number] => 19/273567 [patent_app_country] => US [patent_app_date] => 2025-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19273567 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/273567
Systems and methods for implementing directional operand broadcast and multiply-accumulate execution using a configurable patch mesh in a multi-core processing array of an integrated circuit Jul 17, 2025 Issued
Array ( [id] => 20310721 [patent_doc_number] => 20250328350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => Branch Status Table and Control Instruction Buffer for Processor Instruction Pipeline [patent_app_type] => utility [patent_app_number] => 19/018392 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018392 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018392
Branch Status Table and Control Instruction Buffer for Processor Instruction Pipeline Jan 12, 2025 Pending
Array ( [id] => 19992588 [patent_doc_number] => 20250130810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => SHADER INPUT DATA PROCESSING METHOD AND GRAPHICS PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 19/001115 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001115 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001115
SHADER INPUT DATA PROCESSING METHOD AND GRAPHICS PROCESSING APPARATUS Dec 23, 2024 Pending
Array ( [id] => 19992584 [patent_doc_number] => 20250130806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Implicit Global Pointer Relative Addressing for Global Memory Access [patent_app_type] => utility [patent_app_number] => 18/990578 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18990578 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/990578
Implicit Global Pointer Relative Addressing for Global Memory Access Dec 19, 2024 Pending
Array ( [id] => 19849028 [patent_doc_number] => 20250094379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => DATA-FLOW-DRIVEN RECONFIGURABLE PROCESSOR CHIP AND RECONFIGURABLE PROCESSOR CLUSTER [patent_app_type] => utility [patent_app_number] => 18/971323 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971323
DATA-FLOW-DRIVEN RECONFIGURABLE PROCESSOR CHIP AND RECONFIGURABLE PROCESSOR CLUSTER Dec 5, 2024 Pending
Array ( [id] => 20027892 [patent_doc_number] => 20250166114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/967123 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967123
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY Dec 2, 2024 Pending
Array ( [id] => 19865394 [patent_doc_number] => 20250104180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/967172 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967172
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY Dec 2, 2024 Pending
Array ( [id] => 20380426 [patent_doc_number] => 20250362919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => METHOD FOR PROCESSING INSTRUCTION, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/952665 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/952665
METHOD FOR PROCESSING INSTRUCTION, DEVICE, AND STORAGE MEDIUM Nov 18, 2024 Pending
Array ( [id] => 19725754 [patent_doc_number] => 20250028505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => ACCELERATING 2D CONVOLUTIONAL LAYER MAPPING ON A DOT PRODUCT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/908555 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908555
ACCELERATING 2D CONVOLUTIONAL LAYER MAPPING ON A DOT PRODUCT ARCHITECTURE Oct 6, 2024 Pending
Array ( [id] => 19725814 [patent_doc_number] => 20250028565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/906648 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906648
SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS Oct 3, 2024 Pending
Array ( [id] => 19864763 [patent_doc_number] => 20250103549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, PROCESSOR, ELECTRONIC DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/896789 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/896789
Improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor Sep 24, 2024 Issued
Array ( [id] => 20570489 [patent_doc_number] => 20260064413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => STORAGE INSTRUCTION FOR MATRIX MULTIPLY-ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/819931 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 72625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819931
STORAGE INSTRUCTION FOR MATRIX MULTIPLY-ACCUMULATE OPERATIONS Aug 28, 2024 Pending
Array ( [id] => 20446898 [patent_doc_number] => 20260003620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => PROCESSING FOR PROCESSORS PERFORMING TASKS INVOLVING LOOPS [patent_app_type] => utility [patent_app_number] => 18/759637 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759637
PROCESSING FOR PROCESSORS PERFORMING TASKS INVOLVING LOOPS Jun 27, 2024 Pending
Array ( [id] => 19482195 [patent_doc_number] => 20240330237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/743637 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743637
Context load mechanism in a coarse-grained reconfigurable array processor Jun 13, 2024 Issued
Array ( [id] => 19481948 [patent_doc_number] => 20240329990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Processing of Synchronization Barrier Instructions [patent_app_type] => utility [patent_app_number] => 18/740430 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740430
Processing of Synchronization Barrier Instructions Jun 10, 2024 Pending
Array ( [id] => 20351462 [patent_doc_number] => 20250348314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => QUANTUM COMPUTER WITH A PRACTICAL-SCALE INSTRUCTION HIERARCHY [patent_app_type] => utility [patent_app_number] => 18/656902 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656902
Quantum computer with a practical-scale instruction hierarchy May 6, 2024 Issued
Array ( [id] => 19383187 [patent_doc_number] => 20240273057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors [patent_app_type] => utility [patent_app_number] => 18/635114 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635114
Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors Apr 14, 2024 Pending
Array ( [id] => 20290020 [patent_doc_number] => 20250315263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => Trace Cache Access Prediction and Read Enable [patent_app_type] => utility [patent_app_number] => 18/627035 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627035
Trace cache access prediction and read enable Apr 3, 2024 Issued
Array ( [id] => 20290019 [patent_doc_number] => 20250315262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => Hierarchical Trace Cache [patent_app_type] => utility [patent_app_number] => 18/626929 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626929 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626929
Hierarchical Trace Cache Apr 3, 2024 Pending
Array ( [id] => 20249743 [patent_doc_number] => 20250298612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => APPARATUS AND METHOD FOR HIDING VECTOR LOAD LATENCY IN A TIME-BASED VECTOR COPROCESSOR [patent_app_type] => utility [patent_app_number] => 18/609945 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609945
APPARATUS AND METHOD FOR HIDING VECTOR LOAD LATENCY IN A TIME-BASED VECTOR COPROCESSOR Mar 18, 2024 Pending
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