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Scott Rand

Examiner (ID: 15889)

Most Active Art Unit
1209
Art Unit(s)
1209
Total Applications
286
Issued Applications
196
Pending Applications
9
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17984573 [patent_doc_number] => 20220350610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => Method Of Debugging A Processor That Executes Vertices Of an Application, Each Vertex Being Assigned To a Programming Thread of the Processor [patent_app_type] => utility [patent_app_number] => 17/812214 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812214
Method of debugging a processor that executes vertices of an application, each vertex being assigned to a programming thread of the processor Jul 12, 2022 Issued
Array ( [id] => 18881293 [patent_doc_number] => 20240004662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => INSTRUCTIONS AND SUPPORT FOR HORIZONTAL REDUCTIONS [patent_app_type] => utility [patent_app_number] => 17/856978 [patent_app_country] => US [patent_app_date] => 2022-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856978
INSTRUCTIONS AND SUPPORT FOR HORIZONTAL REDUCTIONS Jul 1, 2022 Pending
Array ( [id] => 18038339 [patent_doc_number] => 20220382555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MIXED INFERENCE USING LOW AND HIGH PRECISION [patent_app_type] => utility [patent_app_number] => 17/839856 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839856
Concurrent multi-datatype execution within a processing resource Jun 13, 2022 Issued
Array ( [id] => 17794227 [patent_doc_number] => 20220253319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => Hardware Unit for Performing Matrix Multiplication with Clock Gating [patent_app_type] => utility [patent_app_number] => 17/733386 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733386
Hardware unit for performing matrix multiplication with clock gating Apr 28, 2022 Issued
Array ( [id] => 18711227 [patent_doc_number] => 20230333856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => Load-Store Unit Dual Tags and Replays [patent_app_type] => utility [patent_app_number] => 17/659569 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659569
Load-store unit dual tags and replays Apr 17, 2022 Issued
Array ( [id] => 19220034 [patent_doc_number] => 20240184738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => CONFIGURABLE MEMORY POOL SYSTEM [patent_app_type] => utility [patent_app_number] => 18/554963 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18554963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/554963
CONFIGURABLE MEMORY POOL SYSTEM Apr 12, 2022 Pending
Array ( [id] => 18677820 [patent_doc_number] => 20230315467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => STORING INSTRUCTIONS FROM SECOND STORAGE TO FIRST STORAGE WHILE FETCH OPERATION IS STALLED, AND READING INSTRUCTIONS FROM FIRST INSTRUCTION STORAGE UPON RESUMING FETCH OPERATION [patent_app_type] => utility [patent_app_number] => 17/712103 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712103
STORING INSTRUCTIONS FROM SECOND STORAGE TO FIRST STORAGE WHILE FETCH OPERATION IS STALLED, AND READING INSTRUCTIONS FROM FIRST INSTRUCTION STORAGE UPON RESUMING FETCH OPERATION Apr 1, 2022 Pending
Array ( [id] => 18677826 [patent_doc_number] => 20230315473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS [patent_app_type] => utility [patent_app_number] => 17/712139 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712139
VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS Apr 1, 2022 Pending
Array ( [id] => 18677822 [patent_doc_number] => 20230315469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => HYBRID PARALLELIZED TAGGED GEOMETRIC (TAGE) BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 17/708344 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708344
Hybrid parallelized tagged geometric (TAGE) branch prediction Mar 29, 2022 Issued
Array ( [id] => 18659985 [patent_doc_number] => 20230305992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => PROCESSOR USING TARGET INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/704122 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704122
PROCESSOR USING TARGET INSTRUCTIONS Mar 24, 2022 Abandoned
Array ( [id] => 18400878 [patent_doc_number] => 11663016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory [patent_app_type] => utility [patent_app_number] => 17/701749 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 15677 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701749
IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory Mar 22, 2022 Issued
Array ( [id] => 18149745 [patent_doc_number] => 20230023602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/699217 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699217
ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD Mar 20, 2022 Abandoned
Array ( [id] => 18022761 [patent_doc_number] => 20220374260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/686404 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686404
SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS Mar 2, 2022 Pending
Array ( [id] => 18592008 [patent_doc_number] => 11740906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Methods and systems for nested stream prefetching for general purpose central processing units [patent_app_type] => utility [patent_app_number] => 17/677413 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8593 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17677413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/677413
Methods and systems for nested stream prefetching for general purpose central processing units Feb 21, 2022 Issued
Array ( [id] => 17763379 [patent_doc_number] => 20220236991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => APPARATUS AND METHOD FOR VECTOR HORIZONTAL ADD OF SIGNED/UNSIGNED WORDS AND DOUBLEWORDS [patent_app_type] => utility [patent_app_number] => 17/671356 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671356
APPARATUS AND METHOD FOR VECTOR HORIZONTAL ADD OF SIGNED/UNSIGNED WORDS AND DOUBLEWORDS Feb 13, 2022 Abandoned
Array ( [id] => 18262160 [patent_doc_number] => 11609862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Method and apparatus to sort a vector for a bitonic sorting algorithm [patent_app_type] => utility [patent_app_number] => 17/665958 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 55 [patent_no_of_words] => 32283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665958
Method and apparatus to sort a vector for a bitonic sorting algorithm Feb 6, 2022 Issued
Array ( [id] => 18330715 [patent_doc_number] => 11635957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Hardware-implemented universal floating-point instruction set architecture for computing directly with human-readable decimal character sequence floating-point representation operands [patent_app_type] => utility [patent_app_number] => 17/591963 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 89 [patent_figures_cnt] => 95 [patent_no_of_words] => 49916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591963
Hardware-implemented universal floating-point instruction set architecture for computing directly with human-readable decimal character sequence floating-point representation operands Feb 2, 2022 Issued
Array ( [id] => 18119196 [patent_doc_number] => 11550590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => System and method for implementing strong load ordering in a processor using a circular ordering ring [patent_app_type] => utility [patent_app_number] => 17/587719 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8093 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587719
System and method for implementing strong load ordering in a processor using a circular ordering ring Jan 27, 2022 Issued
Array ( [id] => 19434583 [patent_doc_number] => 20240303081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Parallel Decode Instruction Set Computer Architecture with Variable-Length Instructions [patent_app_type] => utility [patent_app_number] => 18/549853 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18549853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/549853
Parallel Decode Instruction Set Computer Architecture with Variable-Length Instructions Jan 25, 2022 Pending
Array ( [id] => 18136247 [patent_doc_number] => 11561926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Data exchange pathways between pairs of processing units in columns in a computer [patent_app_type] => utility [patent_app_number] => 17/648517 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 16246 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648517
Data exchange pathways between pairs of processing units in columns in a computer Jan 19, 2022 Issued
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