Scott T. Baderman

Array ( [id] => 1506071 [patent_doc_number] => 06487679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Error recovery mechanism for a high-performance interconnect' [patent_app_type] => B1 [patent_app_number] => 09/437041 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487679.pdf [firstpage_image] =>[orig_patent_app_number] => 09437041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1506078 [patent_doc_number] => 06487681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'In-sheet transceiver testing' [patent_app_type] => B1 [patent_app_number] => 09/437718 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487681.pdf [firstpage_image] =>[orig_patent_app_number] => 09437718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423981 [patent_doc_number] => 06539502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method and apparatus for identifying instructions for performance monitoring in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/436109 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8017 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539502.pdf [firstpage_image] =>[orig_patent_app_number] => 09436109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429599 [patent_doc_number] => 06530042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method and apparatus for monitoring the performance of internal queues in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/436108 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5471 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530042.pdf [firstpage_image] =>[orig_patent_app_number] => 09436108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1319348 [patent_doc_number] => 06618824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method and apparatus for modifying relocatable object code files and monitoring programs' [patent_app_type] => B1 [patent_app_number] => 09/434203 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7719 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618824.pdf [firstpage_image] =>[orig_patent_app_number] => 09434203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1097493 [patent_doc_number] => 06826715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Automatic capture and comparison of computer configuration data' [patent_app_type] => B1 [patent_app_number] => 09/429226 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7381 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826715.pdf [firstpage_image] =>[orig_patent_app_number] => 09429226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444183 [patent_doc_number] => 06496947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Built-in self repair circuit with pause for data retention coverage' [patent_app_type] => B1 [patent_app_number] => 09/426034 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5118 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496947.pdf [firstpage_image] =>[orig_patent_app_number] => 09426034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430064 [patent_doc_number] => 06510531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Methods and systems for testing parallel queues' [patent_app_type] => B1 [patent_app_number] => 09/401897 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13955 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510531.pdf [firstpage_image] =>[orig_patent_app_number] => 09401897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429535 [patent_doc_number] => 06530032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Network fault recovery method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/401919 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 6536 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530032.pdf [firstpage_image] =>[orig_patent_app_number] => 09401919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430059 [patent_doc_number] => 06510530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'At-speed built-in self testing of multi-port compact sRAMs' [patent_app_type] => B1 [patent_app_number] => 09/401976 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7403 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510530.pdf [firstpage_image] =>[orig_patent_app_number] => 09401976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5861409 [patent_doc_number] => 20020124212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'WATCHDOG CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/381777 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1343 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124212.pdf [firstpage_image] =>[orig_patent_app_number] => 09381777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429587 [patent_doc_number] => 06530040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Parallel test in asynchronous memory with single-ended output path' [patent_app_type] => B1 [patent_app_number] => 09/401614 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5491 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530040.pdf [firstpage_image] =>[orig_patent_app_number] => 09401614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431557 [patent_doc_number] => 06519716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Electronic device initialization with dynamic selection of access time for non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/400587 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519716.pdf [firstpage_image] =>[orig_patent_app_number] => 09400587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1417279 [patent_doc_number] => 06532548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'System and method for handling temporary errors on a redundant array of independent tapes (RAIT)' [patent_app_type] => B1 [patent_app_number] => 09/400652 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3959 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532548.pdf [firstpage_image] =>[orig_patent_app_number] => 09400652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1353931 [patent_doc_number] => 06594787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Input/output device managed timer process' [patent_app_type] => B1 [patent_app_number] => 09/399437 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4643 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594787.pdf [firstpage_image] =>[orig_patent_app_number] => 09399437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324346 [patent_doc_number] => 06189104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Integrated network security access control system' [patent_app_type] => 1 [patent_app_number] => 9/391306 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3533 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189104.pdf [firstpage_image] =>[orig_patent_app_number] => 391306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4295019 [patent_doc_number] => 06324647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'System, method and article of manufacture for security management in a development architecture framework' [patent_app_type] => 1 [patent_app_number] => 9/388137 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 14 [patent_no_of_words] => 68255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324647.pdf [firstpage_image] =>[orig_patent_app_number] => 388137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4335849 [patent_doc_number] => 06243834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Apparatus and method for capturing information off a plurality of bi-directional communications buses' [patent_app_type] => 1 [patent_app_number] => 9/383821 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3776 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243834.pdf [firstpage_image] =>[orig_patent_app_number] => 383821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1540686 [patent_doc_number] => 06490697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Diagnosing apparatus and method for RAM' [patent_app_type] => B1 [patent_app_number] => 09/384403 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2897 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490697.pdf [firstpage_image] =>[orig_patent_app_number] => 09384403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431421 [patent_doc_number] => 06523135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Built-in self-test circuit for a memory device' [patent_app_type] => B1 [patent_app_number] => 09/383207 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5248 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523135.pdf [firstpage_image] =>[orig_patent_app_number] => 09383207 [rel_patent_id] =>[rel_patent_doc_number] =>)