Search

Scott T. Baderman

Supervisory Patent Examiner (ID: 7196, Phone: (571)272-3644 , Office: P/2144 )

Most Active Art Unit
2785
Art Unit(s)
2785, 2184, 2114, 2144, 2413, 2113, 2118
Total Applications
584
Issued Applications
474
Pending Applications
52
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1052632 [patent_doc_number] => 06862690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Hierarchical recovery method for fibre-channel devices' [patent_app_type] => utility [patent_app_number] => 09/882707 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862690.pdf [firstpage_image] =>[orig_patent_app_number] => 09882707 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882707
Hierarchical recovery method for fibre-channel devices Jun 14, 2001 Issued
Array ( [id] => 786110 [patent_doc_number] => 06993677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-31 [patent_title] => 'System and method for data verification in a RAID system' [patent_app_type] => utility [patent_app_number] => 09/881584 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3059 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993677.pdf [firstpage_image] =>[orig_patent_app_number] => 09881584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881584
System and method for data verification in a RAID system Jun 13, 2001 Issued
Array ( [id] => 1097498 [patent_doc_number] => 06826717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Synchronization of hardware and software debuggers' [patent_app_type] => B1 [patent_app_number] => 09/880692 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12514 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826717.pdf [firstpage_image] =>[orig_patent_app_number] => 09880692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880692
Synchronization of hardware and software debuggers Jun 11, 2001 Issued
Array ( [id] => 6265472 [patent_doc_number] => 20020188836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Fault resistant operating system' [patent_app_type] => new [patent_app_number] => 09/881007 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3929 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188836.pdf [firstpage_image] =>[orig_patent_app_number] => 09881007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881007
Fault resistant operating system Jun 11, 2001 Issued
Array ( [id] => 7016210 [patent_doc_number] => 20010052090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Storage device having an error correction function' [patent_app_type] => new [patent_app_number] => 09/878053 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3029 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052090.pdf [firstpage_image] =>[orig_patent_app_number] => 09878053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878053
Storage device having an error correction function Jun 7, 2001 Abandoned
Array ( [id] => 7618396 [patent_doc_number] => 06944797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method and system for tracing' [patent_app_type] => utility [patent_app_number] => 09/876689 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4011 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944797.pdf [firstpage_image] =>[orig_patent_app_number] => 09876689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/876689
Method and system for tracing Jun 6, 2001 Issued
Array ( [id] => 6883329 [patent_doc_number] => 20010049801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Dual-ported operator control panel with automatic failover' [patent_app_type] => new [patent_app_number] => 09/862904 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7380 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049801.pdf [firstpage_image] =>[orig_patent_app_number] => 09862904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862904
Dual-ported operator control panel with automatic failover May 21, 2001 Abandoned
Array ( [id] => 1466479 [patent_doc_number] => 06393587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Deep trace memory system for a protocol analyzer' [patent_app_type] => B1 [patent_app_number] => 09/848128 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393587.pdf [firstpage_image] =>[orig_patent_app_number] => 09848128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/848128
Deep trace memory system for a protocol analyzer May 2, 2001 Issued
Array ( [id] => 1218299 [patent_doc_number] => 06711700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method and apparatus to monitor the run state of a multi-partitioned computer system' [patent_app_type] => B2 [patent_app_number] => 09/840345 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3400 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711700.pdf [firstpage_image] =>[orig_patent_app_number] => 09840345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840345
Method and apparatus to monitor the run state of a multi-partitioned computer system Apr 22, 2001 Issued
Array ( [id] => 1221816 [patent_doc_number] => 06708284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Method and apparatus for improving reliability in microprocessors' [patent_app_type] => B2 [patent_app_number] => 09/820703 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4235 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708284.pdf [firstpage_image] =>[orig_patent_app_number] => 09820703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820703
Method and apparatus for improving reliability in microprocessors Mar 29, 2001 Issued
Array ( [id] => 6896755 [patent_doc_number] => 20010027545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Circuit and method, for storing data prior to and after determining failure' [patent_app_type] => new [patent_app_number] => 09/818785 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5235 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027545.pdf [firstpage_image] =>[orig_patent_app_number] => 09818785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818785
Circuit and method, for storing data prior to and after determining failure Mar 27, 2001 Issued
Array ( [id] => 7029690 [patent_doc_number] => 20010014921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Control system using plural objects, a programming method therefor, and a peripheral devices control system' [patent_app_type] => new [patent_app_number] => 09/819217 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9426 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014921.pdf [firstpage_image] =>[orig_patent_app_number] => 09819217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819217
Control system using plural objects, a programming method therefor, and a peripheral devices control system Mar 26, 2001 Issued
Array ( [id] => 7642334 [patent_doc_number] => 06430712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and apparatus for inter-domain alarm correlation' [patent_app_type] => B2 [patent_app_number] => 09/811748 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7663 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430712.pdf [firstpage_image] =>[orig_patent_app_number] => 09811748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811748
Method and apparatus for inter-domain alarm correlation Mar 18, 2001 Issued
Array ( [id] => 5848523 [patent_doc_number] => 20020133745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Self-checking multi-threaded processor' [patent_app_type] => new [patent_app_number] => 09/812125 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3934 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133745.pdf [firstpage_image] =>[orig_patent_app_number] => 09812125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812125
Self-checking multi-threaded processor Mar 18, 2001 Issued
Array ( [id] => 1071026 [patent_doc_number] => 06845471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Apparatus for and method of action synchronization for software reproducibility' [patent_app_type] => utility [patent_app_number] => 09/797797 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4503 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845471.pdf [firstpage_image] =>[orig_patent_app_number] => 09797797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797797
Apparatus for and method of action synchronization for software reproducibility Mar 1, 2001 Issued
Array ( [id] => 7095141 [patent_doc_number] => 20010034859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Configurable debug system with wire list walking' [patent_app_type] => new [patent_app_number] => 09/798001 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12274 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034859.pdf [firstpage_image] =>[orig_patent_app_number] => 09798001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798001
Configurable debug system with wire list walking Mar 1, 2001 Issued
Array ( [id] => 1186451 [patent_doc_number] => 06742145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Method of de-allocating multiple processor cores for an L2 correctable error' [patent_app_type] => B2 [patent_app_number] => 09/798161 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3030 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742145.pdf [firstpage_image] =>[orig_patent_app_number] => 09798161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798161
Method of de-allocating multiple processor cores for an L2 correctable error Feb 28, 2001 Issued
Array ( [id] => 6181218 [patent_doc_number] => 20020156954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Apparatus and methods for identifying bus protocol violations' [patent_app_type] => new [patent_app_number] => 09/796155 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6730 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156954.pdf [firstpage_image] =>[orig_patent_app_number] => 09796155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796155
Apparatus and methods for identifying bus protocol violations Feb 27, 2001 Issued
Array ( [id] => 1116715 [patent_doc_number] => 06804794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Error condition handling' [patent_app_type] => B1 [patent_app_number] => 09/796259 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804794.pdf [firstpage_image] =>[orig_patent_app_number] => 09796259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796259
Error condition handling Feb 27, 2001 Issued
Array ( [id] => 1125020 [patent_doc_number] => 06799284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Reparity bitmap RAID failure recovery' [patent_app_type] => B1 [patent_app_number] => 09/797007 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4445 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799284.pdf [firstpage_image] =>[orig_patent_app_number] => 09797007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797007
Reparity bitmap RAID failure recovery Feb 27, 2001 Issued
Menu