Search

Sean D. Rossiter

Examiner (ID: 5050, Phone: (571)270-3788 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2133, 2186
Total Applications
967
Issued Applications
871
Pending Applications
36
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20234177 [patent_doc_number] => 20250291496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD FOR MULTI-PLANE PROGRAM THEREOF [patent_app_type] => utility [patent_app_number] => 19/223044 [patent_app_country] => US [patent_app_date] => 2025-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19223044 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/223044
MEMORY SYSTEM AND OPERATING METHOD FOR MULTI-PLANE PROGRAM THEREOF May 29, 2025 Pending
Array ( [id] => 20181230 [patent_doc_number] => 20250265188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MEMORY SYSTEM WHICH ORDERS DATA FETCHING FROM A LATCH CIRCUIT DURING EXECUTION OF A READ OPERATION [patent_app_type] => utility [patent_app_number] => 19/196008 [patent_app_country] => US [patent_app_date] => 2025-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19196008 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/196008
MEMORY SYSTEM WHICH ORDERS DATA FETCHING FROM A LATCH CIRCUIT DURING EXECUTION OF A READ OPERATION Apr 30, 2025 Pending
Array ( [id] => 20249669 [patent_doc_number] => 20250298538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TECHNIQUES FOR PRIORITY INFORMATION [patent_app_type] => utility [patent_app_number] => 19/072736 [patent_app_country] => US [patent_app_date] => 2025-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19072736 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/072736
TECHNIQUES FOR PRIORITY INFORMATION Mar 5, 2025 Pending
Array ( [id] => 20221702 [patent_doc_number] => 20250284633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => MEMORY DEVICE WITH DUAL LOGIC INTERFACES AND INTERNAL DATA MOVER [patent_app_type] => utility [patent_app_number] => 19/060360 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060360 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/060360
MEMORY DEVICE WITH DUAL LOGIC INTERFACES AND INTERNAL DATA MOVER Feb 20, 2025 Pending
Array ( [id] => 20513030 [patent_doc_number] => 20260037131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => SYSTEMS AND METHODS OF DATA STAGING FOR DRAM TIMING COMPLIANCE IN NAND MEMORY [patent_app_type] => utility [patent_app_number] => 19/060623 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060623 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/060623
SYSTEMS AND METHODS OF DATA STAGING FOR DRAM TIMING COMPLIANCE IN NAND MEMORY Feb 20, 2025 Pending
Array ( [id] => 20221502 [patent_doc_number] => 20250284433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => MULTI-PLANE PRE-READ FOR SEQUENTIAL READ PERFORMANCE [patent_app_type] => utility [patent_app_number] => 19/059104 [patent_app_country] => US [patent_app_date] => 2025-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19059104 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/059104
MULTI-PLANE PRE-READ FOR SEQUENTIAL READ PERFORMANCE Feb 19, 2025 Pending
Array ( [id] => 20094949 [patent_doc_number] => 20250224885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => Maintenance Operations in a DRAM [patent_app_type] => utility [patent_app_number] => 19/026093 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19026093 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/026093
Maintenance Operations in a DRAM Jan 15, 2025 Issued
Array ( [id] => 20017852 [patent_doc_number] => 20250156074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => Determining Storage Capacity Utilization Based On Deduplicated Data [patent_app_type] => utility [patent_app_number] => 19/022423 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022423 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/022423
Fractional storage capacity utilization based on deduplicated data Jan 14, 2025 Issued
Array ( [id] => 20695502 [patent_doc_number] => 20260126914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => FLASH MEMORY CONTROLLER AND DATA READING METHOD OF FLASH MEMORY CONTROLLER CAPABLE OF ENHANCING AND MAXIMIZING PERFORMANCE OF READ OPERATIONS [patent_app_type] => utility [patent_app_number] => 19/008583 [patent_app_country] => US [patent_app_date] => 2025-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008583 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/008583
Flash memory controller and data reading method of flash memory controller capable of enhancing and maximizing performance of read operations Jan 1, 2025 Issued
Array ( [id] => 20395153 [patent_doc_number] => 20250370628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY DEVICE, SYSTEM-ON-CHIP CONFIGURED TO CONTROL MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 19/001725 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001725 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001725
MEMORY DEVICE, SYSTEM-ON-CHIP CONFIGURED TO CONTROL MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME Dec 25, 2024 Pending
Array ( [id] => 20094936 [patent_doc_number] => 20250224872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS [patent_app_type] => utility [patent_app_number] => 19/001067 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001067 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001067
APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS Dec 23, 2024 Pending
Array ( [id] => 20487283 [patent_doc_number] => 20260023482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => MEMORY CONTROLLER FOR MEMORY WITH MEDIUM GRANULARITY REFRESH COMMANDS [patent_app_type] => utility [patent_app_number] => 19/000151 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19000151 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/000151
MEMORY CONTROLLER FOR MEMORY WITH MEDIUM GRANULARITY REFRESH COMMANDS Dec 22, 2024 Pending
Array ( [id] => 20070770 [patent_doc_number] => 20250208992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION [patent_app_type] => utility [patent_app_number] => 18/982336 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/982336
WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION Dec 15, 2024 Pending
Array ( [id] => 20764301 [patent_doc_number] => 20260161284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-11 [patent_title] => ATOMIC MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/973733 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973733
ATOMIC MEMORY OPERATIONS Dec 8, 2024 Pending
Array ( [id] => 19864547 [patent_doc_number] => 20250103333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/971484 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971484
Memory mapping for memory, memory modules, and non-volatile memory Dec 5, 2024 Issued
Array ( [id] => 19849002 [patent_doc_number] => 20250094353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Memory Migration and Page Fault Avoidance [patent_app_type] => utility [patent_app_number] => 18/965439 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/965439
Memory migration and page fault avoidance Dec 1, 2024 Issued
Array ( [id] => 19834073 [patent_doc_number] => 20250085859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => CONTROLLER ARCHITECTURE FOR RELIABILITY, AVAILABILITY, SERVICEABILITY ACCESS [patent_app_type] => utility [patent_app_number] => 18/955554 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/955554
CONTROLLER ARCHITECTURE FOR RELIABILITY, AVAILABILITY, SERVICEABILITY ACCESS Nov 20, 2024 Pending
Array ( [id] => 19787203 [patent_doc_number] => 20250060882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => Data Storage Device That Detects and Releases Bottlenecks in Hardware [patent_app_type] => utility [patent_app_number] => 18/937415 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/937415
Data Storage Device That Detects and Releases Bottlenecks in Hardware Nov 4, 2024 Pending
Array ( [id] => 20087104 [patent_doc_number] => 20250217040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => COMPUTING DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/935606 [patent_app_country] => US [patent_app_date] => 2024-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935606
Computing device and method thereof for a promotion method in a tiered memory system Nov 2, 2024 Issued
Array ( [id] => 20550461 [patent_doc_number] => 12561254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Memory device for configuring mapping table and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/934498 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18934498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/934498
Memory device for configuring mapping table and operating method thereof Oct 31, 2024 Issued
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