
Sean D. Rossiter
Examiner (ID: 5301)
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2133, 2186 |
| Total Applications | 963 |
| Issued Applications | 865 |
| Pending Applications | 38 |
| Abandoned Applications | 79 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20249669
[patent_doc_number] => 20250298538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => TECHNIQUES FOR PRIORITY INFORMATION
[patent_app_type] => utility
[patent_app_number] => 19/072736
[patent_app_country] => US
[patent_app_date] => 2025-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8420
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19072736
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/072736 | TECHNIQUES FOR PRIORITY INFORMATION | Mar 5, 2025 | Pending |
Array
(
[id] => 20221702
[patent_doc_number] => 20250284633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => MEMORY DEVICE WITH DUAL LOGIC INTERFACES AND INTERNAL DATA MOVER
[patent_app_type] => utility
[patent_app_number] => 19/060360
[patent_app_country] => US
[patent_app_date] => 2025-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3698
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060360
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/060360 | MEMORY DEVICE WITH DUAL LOGIC INTERFACES AND INTERNAL DATA MOVER | Feb 20, 2025 | Pending |
Array
(
[id] => 20221502
[patent_doc_number] => 20250284433
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => MULTI-PLANE PRE-READ FOR SEQUENTIAL READ PERFORMANCE
[patent_app_type] => utility
[patent_app_number] => 19/059104
[patent_app_country] => US
[patent_app_date] => 2025-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11180
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19059104
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/059104 | MULTI-PLANE PRE-READ FOR SEQUENTIAL READ PERFORMANCE | Feb 19, 2025 | Pending |
Array
(
[id] => 20094949
[patent_doc_number] => 20250224885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-10
[patent_title] => Maintenance Operations in a DRAM
[patent_app_type] => utility
[patent_app_number] => 19/026093
[patent_app_country] => US
[patent_app_date] => 2025-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8962
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19026093
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/026093 | Maintenance Operations in a DRAM | Jan 15, 2025 | Pending |
Array
(
[id] => 20017852
[patent_doc_number] => 20250156074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => Determining Storage Capacity Utilization Based On Deduplicated Data
[patent_app_type] => utility
[patent_app_number] => 19/022423
[patent_app_country] => US
[patent_app_date] => 2025-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022423
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/022423 | Determining Storage Capacity Utilization Based On Deduplicated Data | Jan 14, 2025 | Pending |
Array
(
[id] => 20695502
[patent_doc_number] => 20260126914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-05-07
[patent_title] => FLASH MEMORY CONTROLLER AND DATA READING METHOD OF FLASH MEMORY CONTROLLER CAPABLE OF ENHANCING AND MAXIMIZING PERFORMANCE OF READ OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 19/008583
[patent_app_country] => US
[patent_app_date] => 2025-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2623
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008583
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/008583 | FLASH MEMORY CONTROLLER AND DATA READING METHOD OF FLASH MEMORY CONTROLLER CAPABLE OF ENHANCING AND MAXIMIZING PERFORMANCE OF READ OPERATIONS | Jan 1, 2025 | Issued |
Array
(
[id] => 20395153
[patent_doc_number] => 20250370628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => MEMORY DEVICE, SYSTEM-ON-CHIP CONFIGURED TO CONTROL MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 19/001725
[patent_app_country] => US
[patent_app_date] => 2024-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6644
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001725
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/001725 | MEMORY DEVICE, SYSTEM-ON-CHIP CONFIGURED TO CONTROL MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME | Dec 25, 2024 | Pending |
Array
(
[id] => 20094936
[patent_doc_number] => 20250224872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-10
[patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS
[patent_app_type] => utility
[patent_app_number] => 19/001067
[patent_app_country] => US
[patent_app_date] => 2024-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1059
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001067
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/001067 | APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS | Dec 23, 2024 | Pending |
Array
(
[id] => 20487283
[patent_doc_number] => 20260023482
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-22
[patent_title] => MEMORY CONTROLLER FOR MEMORY WITH MEDIUM GRANULARITY REFRESH COMMANDS
[patent_app_type] => utility
[patent_app_number] => 19/000151
[patent_app_country] => US
[patent_app_date] => 2024-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1128
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19000151
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/000151 | MEMORY CONTROLLER FOR MEMORY WITH MEDIUM GRANULARITY REFRESH COMMANDS | Dec 22, 2024 | Pending |
Array
(
[id] => 20070770
[patent_doc_number] => 20250208992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION
[patent_app_type] => utility
[patent_app_number] => 18/982336
[patent_app_country] => US
[patent_app_date] => 2024-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982336
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/982336 | WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION | Dec 15, 2024 | Pending |
Array
(
[id] => 19864547
[patent_doc_number] => 20250103333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/971484
[patent_app_country] => US
[patent_app_date] => 2024-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5732
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971484
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/971484 | Memory mapping for memory, memory modules, and non-volatile memory | Dec 5, 2024 | Issued |
Array
(
[id] => 19849002
[patent_doc_number] => 20250094353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => Memory Migration and Page Fault Avoidance
[patent_app_type] => utility
[patent_app_number] => 18/965439
[patent_app_country] => US
[patent_app_date] => 2024-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7259
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965439
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/965439 | Memory migration and page fault avoidance | Dec 1, 2024 | Issued |
Array
(
[id] => 19834073
[patent_doc_number] => 20250085859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => CONTROLLER ARCHITECTURE FOR RELIABILITY, AVAILABILITY, SERVICEABILITY ACCESS
[patent_app_type] => utility
[patent_app_number] => 18/955554
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9459
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955554
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/955554 | CONTROLLER ARCHITECTURE FOR RELIABILITY, AVAILABILITY, SERVICEABILITY ACCESS | Nov 20, 2024 | Pending |
Array
(
[id] => 19787203
[patent_doc_number] => 20250060882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-20
[patent_title] => Data Storage Device That Detects and Releases Bottlenecks in Hardware
[patent_app_type] => utility
[patent_app_number] => 18/937415
[patent_app_country] => US
[patent_app_date] => 2024-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937415
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/937415 | Data Storage Device That Detects and Releases Bottlenecks in Hardware | Nov 4, 2024 | Pending |
Array
(
[id] => 20087104
[patent_doc_number] => 20250217040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => COMPUTING DEVICE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/935606
[patent_app_country] => US
[patent_app_date] => 2024-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2437
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935606
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/935606 | COMPUTING DEVICE AND METHOD OF OPERATING THE SAME | Nov 2, 2024 | Pending |
Array
(
[id] => 20550461
[patent_doc_number] => 12561254
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Memory device for configuring mapping table and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 18/934498
[patent_app_country] => US
[patent_app_date] => 2024-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3785
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18934498
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/934498 | Memory device for configuring mapping table and operating method thereof | Oct 31, 2024 | Issued |
Array
(
[id] => 20152021
[patent_doc_number] => 20250251859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/930124
[patent_app_country] => US
[patent_app_date] => 2024-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5595
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930124
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/930124 | STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME | Oct 28, 2024 | Pending |
Array
(
[id] => 19711108
[patent_doc_number] => 20250021250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/904319
[patent_app_country] => US
[patent_app_date] => 2024-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904319
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/904319 | Sequential data optimized sub-regions in storage devices | Oct 1, 2024 | Issued |
Array
(
[id] => 20310640
[patent_doc_number] => 20250328269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-23
[patent_title] => SYSTEM AND METHODS FOR MEMORY BLOCK ALLOCATION
[patent_app_type] => utility
[patent_app_number] => 18/830559
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6152
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830559
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/830559 | SYSTEM AND METHODS FOR MEMORY BLOCK ALLOCATION | Sep 9, 2024 | Pending |
Array
(
[id] => 20388019
[patent_doc_number] => 12487745
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Suspending operations of a memory system
[patent_app_type] => utility
[patent_app_number] => 18/830454
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 8374
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830454
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/830454 | Suspending operations of a memory system | Sep 9, 2024 | Issued |