Search

Sean D. Rossiter

Examiner (ID: 15780, Phone: (571)270-3788 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2133, 2186
Total Applications
953
Issued Applications
862
Pending Applications
32
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
19/161110 Method for Writing Data to a Solid State Disk, Apparatus, and Solid State Disk Aug 28, 2025 Pending
Array ( [id] => 20094949 [patent_doc_number] => 20250224885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => Maintenance Operations in a DRAM [patent_app_type] => utility [patent_app_number] => 19/026093 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19026093 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/026093
Maintenance Operations in a DRAM Jan 15, 2025 Pending
Array ( [id] => 20017852 [patent_doc_number] => 20250156074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => Determining Storage Capacity Utilization Based On Deduplicated Data [patent_app_type] => utility [patent_app_number] => 19/022423 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022423 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/022423
Determining Storage Capacity Utilization Based On Deduplicated Data Jan 14, 2025 Pending
Array ( [id] => 20395153 [patent_doc_number] => 20250370628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY DEVICE, SYSTEM-ON-CHIP CONFIGURED TO CONTROL MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 19/001725 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001725 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001725
MEMORY DEVICE, SYSTEM-ON-CHIP CONFIGURED TO CONTROL MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME Dec 25, 2024 Pending
Array ( [id] => 20094936 [patent_doc_number] => 20250224872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS [patent_app_type] => utility [patent_app_number] => 19/001067 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001067 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001067
APPARATUSES, SYSTEMS, AND METHODS FOR LOW LATENCY SELECTION POLICY FOR MEMORY COMMANDS Dec 23, 2024 Pending
Array ( [id] => 20070770 [patent_doc_number] => 20250208992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION [patent_app_type] => utility [patent_app_number] => 18/982336 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/982336
WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION Dec 15, 2024 Pending
Array ( [id] => 19864547 [patent_doc_number] => 20250103333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/971484 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971484
MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY Dec 5, 2024 Issued
Array ( [id] => 19849002 [patent_doc_number] => 20250094353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Memory Migration and Page Fault Avoidance [patent_app_type] => utility [patent_app_number] => 18/965439 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/965439
Memory migration and page fault avoidance Dec 1, 2024 Issued
Array ( [id] => 20087104 [patent_doc_number] => 20250217040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => COMPUTING DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/935606 [patent_app_country] => US [patent_app_date] => 2024-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935606
COMPUTING DEVICE AND METHOD OF OPERATING THE SAME Nov 2, 2024 Pending
Array ( [id] => 20550461 [patent_doc_number] => 12561254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Memory device for configuring mapping table and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/934498 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18934498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/934498
Memory device for configuring mapping table and operating method thereof Oct 31, 2024 Issued
Array ( [id] => 20152021 [patent_doc_number] => 20250251859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/930124 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/930124
STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME Oct 28, 2024 Pending
Array ( [id] => 19711108 [patent_doc_number] => 20250021250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/904319 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904319
SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES Oct 1, 2024 Issued
Array ( [id] => 20388019 [patent_doc_number] => 12487745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Suspending operations of a memory system [patent_app_type] => utility [patent_app_number] => 18/830454 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830454
Suspending operations of a memory system Sep 9, 2024 Issued
Array ( [id] => 20374151 [patent_doc_number] => 12481586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Sequential garbage collection [patent_app_type] => utility [patent_app_number] => 18/821062 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821062
Sequential garbage collection Aug 29, 2024 Issued
Array ( [id] => 19645094 [patent_doc_number] => 20240419614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => Resource-Sensitive Scheduling Of Time-Independent Operations [patent_app_type] => utility [patent_app_number] => 18/821586 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821586
Resource-sensitive scheduling of time-independent operations Aug 29, 2024 Issued
Array ( [id] => 20415757 [patent_doc_number] => 12499043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Writing data to a solid state storage array to accommodate power failure [patent_app_type] => utility [patent_app_number] => 18/818308 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 24569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818308
Writing data to a solid state storage array to accommodate power failure Aug 27, 2024 Issued
Array ( [id] => 19864722 [patent_doc_number] => 20250103508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY MODULE WITH MEMORY-OWNERSHIP EXCHANGE [patent_app_type] => utility [patent_app_number] => 18/812262 [patent_app_country] => US [patent_app_date] => 2024-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18812262 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/812262
MEMORY MODULE WITH MEMORY-OWNERSHIP EXCHANGE Aug 21, 2024 Issued
Array ( [id] => 19588194 [patent_doc_number] => 20240385751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MEMORY BLOCK ERASE PROTOCOL [patent_app_type] => utility [patent_app_number] => 18/787528 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787528
Memory block erase protocol Jul 28, 2024 Issued
Array ( [id] => 19558581 [patent_doc_number] => 20240370373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => TIMED DATA TRANSFER BETWEEN A HOST SYSTEM AND A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/778804 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778804
TIMED DATA TRANSFER BETWEEN A HOST SYSTEM AND A MEMORY SUB-SYSTEM Jul 18, 2024 Pending
Array ( [id] => 20428342 [patent_doc_number] => 20250390434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => COHERENT COMMUNICATION BETWEEN A PROCESSOR CORE AND AN ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/754065 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754065 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754065
Coherent communication between a processor core and an accelerator Jun 24, 2024 Issued
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