Sean D. Rossiter

Array ( [id] => 18949954 [patent_doc_number] => 11893250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-06 [patent_title] => Offset-based memory management for integrated circuits and programmable network devices [patent_app_type] => utility [patent_app_number] => 17/396885 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6916 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18183003 [patent_doc_number] => 20230043733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => MEMORY SUB-SYSTEM DATA MIGRATION [patent_app_type] => utility [patent_app_number] => 17/395695 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18166977 [patent_doc_number] => 20230033584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => METHODS AND SYSTEMS FOR MANAGING RACE CONDITIONS DURING USAGE OF A REMOTE STORAGE LOCATION CACHE IN A NETWORKED STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/387807 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18160940 [patent_doc_number] => 20230027532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => EXPANDING RAID SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/382905 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17337993 [patent_doc_number] => 20220004324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => MEMORY BYPASS FOR ERROR DETECTION AND CORRECTION [patent_app_type] => utility [patent_app_number] => 17/349626 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18136048 [patent_doc_number] => 11561724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => SSD supporting low latency operation [patent_app_type] => utility [patent_app_number] => 17/335650 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6802 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17751389 [patent_doc_number] => 20220229594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/324409 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18014990 [patent_doc_number] => 11507286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Performing storage provision operations on a file system [patent_app_type] => utility [patent_app_number] => 17/323268 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 11590 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18203994 [patent_doc_number] => 11586385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Techniques for managing writes in nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/313926 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 41 [patent_no_of_words] => 39161 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17038810 [patent_doc_number] => 20210255769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SYSTEMS AND METHODS FOR MODIFYING STORAGE SYSTEM CONFIGURATION USING ARTIFICIAL INTELLIGENCE [patent_app_type] => utility [patent_app_number] => 17/308121 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17581003 [patent_doc_number] => 20220137858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING MEMORY CONTROLLER INCLUDED THEREIN [patent_app_type] => utility [patent_app_number] => 17/307325 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17962004 [patent_doc_number] => 20220342585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => USER CONTROLLED DATA-IN FOR LOWER AND MIDDLE PAGE IN MLC-FINE QLC MEMORIES [patent_app_type] => utility [patent_app_number] => 17/236704 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17915755 [patent_doc_number] => 20220318151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => METHOD AND APPARATUS FOR A DRAM CACHE TAG PREFETCHER [patent_app_type] => utility [patent_app_number] => 17/219782 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18430488 [patent_doc_number] => 11675707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Logical to virtual and virtual to physical translation in storage class memory [patent_app_type] => utility [patent_app_number] => 17/214120 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 16164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16934790 [patent_doc_number] => 20210200679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THROUGH A TILE-BASED ADDRESS APERTURE [patent_app_type] => utility [patent_app_number] => 17/204534 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16918783 [patent_doc_number] => 20210191875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => MEMORY SYSTEM FOR BINDING DATA TO A MEMORY NAMESPACE [patent_app_type] => utility [patent_app_number] => 17/192744 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18130044 [patent_doc_number] => 11556251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Apparatuses and methods to control memory operations on buffers [patent_app_type] => utility [patent_app_number] => 17/187066 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17846549 [patent_doc_number] => 11435920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Storage system and method for using read and write buffers in a memory [patent_app_type] => utility [patent_app_number] => 17/183703 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18262009 [patent_doc_number] => 11609710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Host, data storage device, data processing system and data processing method [patent_app_type] => utility [patent_app_number] => 17/177722 [patent_app_country] => US [patent_app_date] => 2021-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18104315 [patent_doc_number] => 11544201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Memory tracing in an emulated computing system [patent_app_type] => utility [patent_app_number] => 17/169042 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7371 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169042 [rel_patent_id] =>[rel_patent_doc_number] =>)