Search

Sean D. Rossiter

Examiner (ID: 15780, Phone: (571)270-3788 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2133, 2186
Total Applications
953
Issued Applications
862
Pending Applications
32
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19905651 [patent_doc_number] => 12282658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-22 [patent_title] => System and method for large memory transaction (LMT) stores [patent_app_type] => utility [patent_app_number] => 18/583457 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3426 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583457
System and method for large memory transaction (LMT) stores Feb 20, 2024 Issued
Array ( [id] => 19891830 [patent_doc_number] => 20250117142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SUSPEND PARAMETER DETERMINATION DEVICE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/581404 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581404 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581404
Suspend parameter determination device and method thereof Feb 19, 2024 Issued
Array ( [id] => 20595174 [patent_doc_number] => 12578890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Block replacement using combined blocks [patent_app_type] => utility [patent_app_number] => 18/438155 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438155
Block replacement using combined blocks Feb 8, 2024 Issued
Array ( [id] => 20331382 [patent_doc_number] => 12461657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Using a zone wordline table to initiate a find last good page process [patent_app_type] => utility [patent_app_number] => 18/436408 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436408
Using a zone wordline table to initiate a find last good page process Feb 7, 2024 Issued
Array ( [id] => 20123341 [patent_doc_number] => 20250238372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => EFFICIENT DEDUPLICATION IN A METADATA DELTA LOG ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/417463 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417463
Efficient deduplication in a metadata delta log architecture Jan 18, 2024 Issued
Array ( [id] => 20174772 [patent_doc_number] => 12393519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Systems and methods for dynamically allocating memory pages to enable memory footprint reduction [patent_app_type] => utility [patent_app_number] => 18/408311 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408311
Systems and methods for dynamically allocating memory pages to enable memory footprint reduction Jan 8, 2024 Issued
Array ( [id] => 19334189 [patent_doc_number] => 20240248619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM [patent_app_type] => utility [patent_app_number] => 18/406687 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406687
Dynamic read retry voltage sequences in a memory subsystem Jan 7, 2024 Issued
Array ( [id] => 20317135 [patent_doc_number] => 12455685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Managing storage resource requirements for storage objects [patent_app_type] => utility [patent_app_number] => 18/399368 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 38527 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399368
Managing storage resource requirements for storage objects Dec 27, 2023 Issued
Array ( [id] => 20087362 [patent_doc_number] => 20250217298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SYSTEMS AND METHODS FOR REDUCING CACHE FILLS [patent_app_type] => utility [patent_app_number] => 18/399332 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399332
Systems and methods for reducing cache fills Dec 27, 2023 Issued
Array ( [id] => 20174597 [patent_doc_number] => 12393343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Memory operation method for unaligned write, memory and electronic device [patent_app_type] => utility [patent_app_number] => 18/397186 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397186
Memory operation method for unaligned write, memory and electronic device Dec 26, 2023 Issued
Array ( [id] => 20130824 [patent_doc_number] => 12373137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Memory controller, memory system, and operating method of memory system [patent_app_type] => utility [patent_app_number] => 18/396041 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 9443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/396041
Memory controller, memory system, and operating method of memory system Dec 25, 2023 Issued
Array ( [id] => 19114706 [patent_doc_number] => 20240126456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => OFFSET-BASED MEMORY MANAGEMENT FOR INTEGRATED CIRCUITS AND PROGRAMMABLE NETWORK DEVICES [patent_app_type] => utility [patent_app_number] => 18/392086 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/392086
Offset-based memory management for integrated circuits and programmable network devices Dec 20, 2023 Issued
Array ( [id] => 19466236 [patent_doc_number] => 20240319906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MULTI-CLUSTER SYSTEM AND MULTI-CLUSTER SYSTEM CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/523905 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523905
Multi-cluster system and multi-cluster system control method Nov 29, 2023 Issued
Array ( [id] => 19159568 [patent_doc_number] => 20240152275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Storage Utilization Determinations in Cloud-Based Storage Systems [patent_app_type] => utility [patent_app_number] => 18/519528 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519528
Storage utilization determinations in cloud-based storage systems Nov 26, 2023 Issued
Array ( [id] => 19413332 [patent_doc_number] => 12079148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Time-independent scheduling of storage operations [patent_app_type] => utility [patent_app_number] => 18/496499 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 35046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/496499
Time-independent scheduling of storage operations Oct 26, 2023 Issued
Array ( [id] => 19426643 [patent_doc_number] => 12086062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Managing power loss in a memory device [patent_app_type] => utility [patent_app_number] => 18/378103 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378103
Managing power loss in a memory device Oct 8, 2023 Issued
Array ( [id] => 19878618 [patent_doc_number] => 20250110875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => LAST LEVEL CACHE HIERARCHY IN CHIPLET BASED PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/374757 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374757 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374757
Last level cache hierarchy in chiplet based processors Sep 28, 2023 Issued
Array ( [id] => 19129293 [patent_doc_number] => 20240134646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/476997 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476997
Memory mapping for memory, memory modules, and non-volatile memory Sep 27, 2023 Issued
Array ( [id] => 19129293 [patent_doc_number] => 20240134646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/476997 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476997
Memory mapping for memory, memory modules, and non-volatile memory Sep 27, 2023 Issued
Array ( [id] => 20647386 [patent_doc_number] => 12602329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Atomic memory operations for address translation [patent_app_type] => utility [patent_app_number] => 18/475310 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475310
ATOMIC MEMORY OPERATIONS FOR ADDRESS TRANSLATION Sep 26, 2023 Issued
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