
Sean D. Rossiter
Examiner (ID: 15780, Phone: (571)270-3788 , Office: P/2133 )
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2133, 2186 |
| Total Applications | 953 |
| Issued Applications | 862 |
| Pending Applications | 32 |
| Abandoned Applications | 79 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9745578
[patent_doc_number] => 20140281297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'MIGRATION OF PEER-MAPPED MEMORY PAGES'
[patent_app_type] => utility
[patent_app_number] => 14/134148
[patent_app_country] => US
[patent_app_date] => 2013-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14379
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134148
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/134148 | Migration of peer-mapped memory pages | Dec 18, 2013 | Issued |
Array
(
[id] => 11193386
[patent_doc_number] => 09424201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-23
[patent_title] => 'Migrating pages of different sizes between heterogeneous processors'
[patent_app_type] => utility
[patent_app_number] => 14/134142
[patent_app_country] => US
[patent_app_date] => 2013-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 12693
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134142
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/134142 | Migrating pages of different sizes between heterogeneous processors | Dec 18, 2013 | Issued |
Array
(
[id] => 10569052
[patent_doc_number] => 09292220
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-22
[patent_title] => 'Method, apparatus, and controller for managing storage array'
[patent_app_type] => utility
[patent_app_number] => 14/134010
[patent_app_country] => US
[patent_app_date] => 2013-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 14106
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134010
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/134010 | Method, apparatus, and controller for managing storage array | Dec 18, 2013 | Issued |
Array
(
[id] => 10124271
[patent_doc_number] => 09158630
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-13
[patent_title] => 'Testing integrity of replicated storage'
[patent_app_type] => utility
[patent_app_number] => 14/133945
[patent_app_country] => US
[patent_app_date] => 2013-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 7662
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133945
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/133945 | Testing integrity of replicated storage | Dec 18, 2013 | Issued |
Array
(
[id] => 9365256
[patent_doc_number] => 20140075129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-13
[patent_title] => 'SYSTEMS AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/079843
[patent_app_country] => US
[patent_app_date] => 2013-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3081
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079843
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/079843 | Systems and methods exchanging data between processors through concurrent shared memory | Nov 13, 2013 | Issued |
Array
(
[id] => 10249769
[patent_doc_number] => 20150134765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-14
[patent_title] => 'POINT-TO-POINT SHARED MEMORY PROTOCOL WITH FEATURE NEGOTIATION'
[patent_app_type] => utility
[patent_app_number] => 14/077036
[patent_app_country] => US
[patent_app_date] => 2013-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4885
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077036
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/077036 | POINT-TO-POINT SHARED MEMORY PROTOCOL WITH FEATURE NEGOTIATION | Nov 10, 2013 | Abandoned |
Array
(
[id] => 9479316
[patent_doc_number] => 20140136779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-15
[patent_title] => 'Method and Apparatus for Achieving Optimal Resource Allocation Dynamically in a Distributed Computing Environment'
[patent_app_type] => utility
[patent_app_number] => 14/076503
[patent_app_country] => US
[patent_app_date] => 2013-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5954
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076503
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/076503 | Method and apparatus for achieving optimal resource allocation dynamically in a distributed computing environment | Nov 10, 2013 | Issued |
Array
(
[id] => 9207542
[patent_doc_number] => 20140006719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'MOBILE MEMORY CACHE READ OPTIMIZATION'
[patent_app_type] => utility
[patent_app_number] => 14/020527
[patent_app_country] => US
[patent_app_date] => 2013-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8532
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020527
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/020527 | Mobile memory cache read optimization | Sep 5, 2013 | Issued |
Array
(
[id] => 10841180
[patent_doc_number] => 08868879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-21
[patent_title] => 'System on chip with reconfigurable SRAM'
[patent_app_type] => utility
[patent_app_number] => 13/971054
[patent_app_country] => US
[patent_app_date] => 2013-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6294
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971054
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/971054 | System on chip with reconfigurable SRAM | Aug 19, 2013 | Issued |
Array
(
[id] => 9826011
[patent_doc_number] => 08935507
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'System and method for storing multiple copies of data in a high speed memory system'
[patent_app_type] => utility
[patent_app_number] => 13/959711
[patent_app_country] => US
[patent_app_date] => 2013-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 55
[patent_no_of_words] => 20725
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13959711
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/959711 | System and method for storing multiple copies of data in a high speed memory system | Aug 4, 2013 | Issued |
Array
(
[id] => 9163448
[patent_doc_number] => 20130311726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-21
[patent_title] => 'SHARED MEMORY TRANSLATION FACILITY'
[patent_app_type] => utility
[patent_app_number] => 13/950446
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3662
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950446
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950446 | Shared memory translation facility | Jul 24, 2013 | Issued |
Array
(
[id] => 9810903
[patent_doc_number] => 20150022849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-22
[patent_title] => 'Method and Apparatus for Optimizing Memory Usage in an Imaging Device'
[patent_app_type] => utility
[patent_app_number] => 13/945744
[patent_app_country] => US
[patent_app_date] => 2013-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6735
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945744
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/945744 | Method and apparatus for optimizing memory usage in an imaging device | Jul 17, 2013 | Issued |
Array
(
[id] => 9430915
[patent_doc_number] => 08707000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-22
[patent_title] => 'Execution of a perform frame management function instruction'
[patent_app_type] => utility
[patent_app_number] => 13/941887
[patent_app_country] => US
[patent_app_date] => 2013-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 18539
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13941887
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/941887 | Execution of a perform frame management function instruction | Jul 14, 2013 | Issued |
Array
(
[id] => 11752176
[patent_doc_number] => 09710187
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-07-18
[patent_title] => 'Managing data relocation in storage systems'
[patent_app_type] => utility
[patent_app_number] => 13/929580
[patent_app_country] => US
[patent_app_date] => 2013-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13929580
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/929580 | Managing data relocation in storage systems | Jun 26, 2013 | Issued |
Array
(
[id] => 9714299
[patent_doc_number] => 08838900
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-16
[patent_title] => 'Atomic-operation coalescing technique in multi-chip systems'
[patent_app_type] => utility
[patent_app_number] => 13/914347
[patent_app_country] => US
[patent_app_date] => 2013-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5885
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13914347
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/914347 | Atomic-operation coalescing technique in multi-chip systems | Jun 9, 2013 | Issued |
Array
(
[id] => 10131065
[patent_doc_number] => 09164900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-20
[patent_title] => 'Methods and systems for expanding preload capabilities of a memory to encompass a register file'
[patent_app_type] => utility
[patent_app_number] => 13/893871
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 4151
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893871
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/893871 | Methods and systems for expanding preload capabilities of a memory to encompass a register file | May 13, 2013 | Issued |
Array
(
[id] => 10041728
[patent_doc_number] => 09082439
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-14
[patent_title] => 'Preventing damage to storage devices within a storage system due to movement of the storage system'
[patent_app_type] => utility
[patent_app_number] => 13/893705
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 8147
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893705
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/893705 | Preventing damage to storage devices within a storage system due to movement of the storage system | May 13, 2013 | Issued |
Array
(
[id] => 10941514
[patent_doc_number] => 20140344535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-20
[patent_title] => 'ACCIDENTAL SHARED VOLUME ERASURE PREVENTION'
[patent_app_type] => utility
[patent_app_number] => 13/894291
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8162
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894291
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/894291 | Accidental shared volume erasure prevention | May 13, 2013 | Issued |
Array
(
[id] => 9056779
[patent_doc_number] => 20130254493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'CACHE MEMORY CAPABLE OF ADJUSTING BURST LENGTH OF WRITE-BACK DATA IN WRITE-BACK OPERATION'
[patent_app_type] => utility
[patent_app_number] => 13/893746
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5878
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893746
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/893746 | Cache memory capable of adjusting burst length of write-back data in write-back operation | May 13, 2013 | Issued |
Array
(
[id] => 9733379
[patent_doc_number] => 20140269088
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'SYSTEM AND METHOD OF READING DATA FROM MEMORY CONCURRENTLY WITH SENDING WRITE DATA TO THE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/875477
[patent_app_country] => US
[patent_app_date] => 2013-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5141
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13875477
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/875477 | System and method of reading data from memory concurrently with sending write data to the memory | May 1, 2013 | Issued |