Search

Sean Mcgarry

Examiner (ID: 7001, Phone: (571)272-0761 , Office: P/1674 )

Most Active Art Unit
1635
Art Unit(s)
1809, 1674, 1624, 1635, 1621, 1805
Total Applications
1931
Issued Applications
1097
Pending Applications
308
Abandoned Applications
560

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18356348 [patent_doc_number] => 11644746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Inverse etch model for mask synthesis [patent_app_type] => utility [patent_app_number] => 17/161345 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161345
Inverse etch model for mask synthesis Jan 27, 2021 Issued
Array ( [id] => 20535230 [patent_doc_number] => 12552288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Battery voltage equalization device [patent_app_type] => utility [patent_app_number] => 17/907258 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1175 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17907258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/907258
Battery voltage equalization device Jan 26, 2021 Issued
Array ( [id] => 18155143 [patent_doc_number] => 11568123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Method for determining an etch profile of a layer of a wafer for a simulation system [patent_app_type] => utility [patent_app_number] => 17/157642 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 22537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157642
Method for determining an etch profile of a layer of a wafer for a simulation system Jan 24, 2021 Issued
Array ( [id] => 18155139 [patent_doc_number] => 11568119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Cell layout of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/151189 [patent_app_country] => US [patent_app_date] => 2021-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151189
Cell layout of semiconductor device Jan 16, 2021 Issued
Array ( [id] => 17231008 [patent_doc_number] => 20210357565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => HYBRID SHEET LAYOUT, METHOD, SYSTEM, AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/147923 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147923
Hybrid sheet layout, method, system, and structure Jan 12, 2021 Issued
Array ( [id] => 18174399 [patent_doc_number] => 11574111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-07 [patent_title] => Electronic design tracing and tamper detection using automatically generated layout patterns [patent_app_type] => utility [patent_app_number] => 17/139876 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139876
Electronic design tracing and tamper detection using automatically generated layout patterns Dec 30, 2020 Issued
Array ( [id] => 18235142 [patent_doc_number] => 11599701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-07 [patent_title] => Method, system, and computer program product for characterizing electronic designs with real-time modeling [patent_app_type] => utility [patent_app_number] => 17/138861 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138861
Method, system, and computer program product for characterizing electronic designs with real-time modeling Dec 29, 2020 Issued
Array ( [id] => 16782196 [patent_doc_number] => 20210119275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD FOR CORRECTING SOC OF BATTERY PACK, BATTERY MANAGEMENT SYSTEM AND VEHICLE [patent_app_type] => utility [patent_app_number] => 17/138433 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138433
Method for correcting SOC of battery pack, battery management system and vehicle Dec 29, 2020 Issued
Array ( [id] => 17786809 [patent_doc_number] => 11409934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Generation of hardware design using a constraint solver module for topology synthesis [patent_app_type] => utility [patent_app_number] => 17/134384 [patent_app_country] => US [patent_app_date] => 2020-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5505 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134384
Generation of hardware design using a constraint solver module for topology synthesis Dec 25, 2020 Issued
Array ( [id] => 16780528 [patent_doc_number] => 20210117607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => High Performance Regularized Network-on-Chip Architecture [patent_app_type] => utility [patent_app_number] => 17/133984 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133984
High performance regularized network-on-chip architecture Dec 23, 2020 Issued
Array ( [id] => 16764517 [patent_doc_number] => 20210110099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS [patent_app_type] => utility [patent_app_number] => 17/132306 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132306
Scalable runtime validation for on-device design rule checks Dec 22, 2020 Issued
Array ( [id] => 17674618 [patent_doc_number] => 20220187785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SYSTEM AND METHOD FOR MACHINE-LEARNING-ENABLED MICRO-OBJECT DENSITY DISTRIBUTION CONTROL WITH THE AID OF A DIGITAL COMPUTER [patent_app_type] => utility [patent_app_number] => 17/122404 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122404
System and method for machine-learning-enabled micro-object density distribution control with the aid of a digital computer Dec 14, 2020 Issued
Array ( [id] => 18119590 [patent_doc_number] => 11550985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Method for automated standard cell design [patent_app_type] => utility [patent_app_number] => 17/122689 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 13348 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122689
Method for automated standard cell design Dec 14, 2020 Issued
Array ( [id] => 16730078 [patent_doc_number] => 20210097225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/117986 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117986
Integrated circuit and method of forming an integrated circuit Dec 9, 2020 Issued
Array ( [id] => 20274000 [patent_doc_number] => 12443783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Logic circuit design method [patent_app_type] => utility [patent_app_number] => 17/786993 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17786993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/786993
Logic circuit design method Dec 8, 2020 Issued
Array ( [id] => 17955427 [patent_doc_number] => 11481536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Method and system for fixing violation of layout [patent_app_type] => utility [patent_app_number] => 17/115668 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115668
Method and system for fixing violation of layout Dec 7, 2020 Issued
Array ( [id] => 16721417 [patent_doc_number] => 20210088564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Authentication, Authorization, And/Or Accounting Of Power-Consuming Devices [patent_app_type] => utility [patent_app_number] => 17/113964 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113964
Authentication, Authorization, And/Or Accounting Of Power-Consuming Devices Dec 6, 2020 Pending
Array ( [id] => 18906600 [patent_doc_number] => 20240022085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => MANAGEMENT SYSTEM AND BATTERY [patent_app_type] => utility [patent_app_number] => 18/254275 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18254275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/254275
MANAGEMENT SYSTEM AND BATTERY Nov 29, 2020 Pending
Array ( [id] => 16857223 [patent_doc_number] => 20210157968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SYSTEMS AND METHODS FOR DETERMINING A CONFIGURATION FOR A MICROARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/107444 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107444
Systems and methods for determining a configuration for a microarchitecture Nov 29, 2020 Issued
Array ( [id] => 17629500 [patent_doc_number] => 20220164515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS [patent_app_type] => utility [patent_app_number] => 17/103748 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103748 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103748
System and method for diagnosing design rule check violations Nov 23, 2020 Issued
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