
Sean Mcgarry
Examiner (ID: 7001, Phone: (571)272-0761 , Office: P/1674 )
| Most Active Art Unit | 1635 |
| Art Unit(s) | 1809, 1674, 1624, 1635, 1621, 1805 |
| Total Applications | 1931 |
| Issued Applications | 1097 |
| Pending Applications | 308 |
| Abandoned Applications | 560 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19857327
[patent_doc_number] => 12260165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture
[patent_app_type] => utility
[patent_app_number] => 18/378384
[patent_app_country] => US
[patent_app_date] => 2023-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10404
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378384
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/378384 | Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture | Oct 9, 2023 | Issued |
Array
(
[id] => 18864575
[patent_doc_number] => 20230419012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => SYSTEMS AND METHODS FOR ELIMINATING ELECTROMIGRATION AND SELF-HEAT VIOLATIONS IN A MASK LAYOUT BLOCK
[patent_app_type] => utility
[patent_app_number] => 18/368038
[patent_app_country] => US
[patent_app_date] => 2023-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368038
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/368038 | SYSTEMS AND METHODS FOR ELIMINATING ELECTROMIGRATION AND SELF-HEAT VIOLATIONS IN A MASK LAYOUT BLOCK | Sep 13, 2023 | Pending |
Array
(
[id] => 19950317
[patent_doc_number] => 12321682
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Post-routing congestion optimization
[patent_app_type] => utility
[patent_app_number] => 18/447567
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 5439
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447567
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447567 | Post-routing congestion optimization | Aug 9, 2023 | Issued |
Array
(
[id] => 20331809
[patent_doc_number] => 12462086
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-04
[patent_title] => Integrated circuit having hybrid sheet structure
[patent_app_type] => utility
[patent_app_number] => 18/448136
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 9619
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448136
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/448136 | Integrated circuit having hybrid sheet structure | Aug 9, 2023 | Issued |
Array
(
[id] => 18811176
[patent_doc_number] => 20230385512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS
[patent_app_type] => utility
[patent_app_number] => 18/447964
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14308
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447964
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447964 | METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS | Aug 9, 2023 | Pending |
Array
(
[id] => 19756113
[patent_doc_number] => 20250044678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-06
[patent_title] => METHOD AND NON-TRANSITORY COMPUTER-READABLE MEDIUM FOR GENERATING LAYOUT BASED ON PATH LABELED WITH MARKER
[patent_app_type] => utility
[patent_app_number] => 18/365250
[patent_app_country] => US
[patent_app_date] => 2023-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7843
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365250
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/365250 | METHOD AND NON-TRANSITORY COMPUTER-READABLE MEDIUM FOR GENERATING LAYOUT BASED ON PATH LABELED WITH MARKER | Aug 3, 2023 | Pending |
Array
(
[id] => 18788241
[patent_doc_number] => 20230376672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => INTEGRATED CIRCUIT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/362946
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17260
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362946 | Integrated circuit structure | Jul 30, 2023 | Issued |
Array
(
[id] => 18810356
[patent_doc_number] => 20230384691
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS
[patent_app_type] => utility
[patent_app_number] => 18/361879
[patent_app_country] => US
[patent_app_date] => 2023-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8030
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361879
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361879 | Optical proximity correction and photomasks | Jul 29, 2023 | Issued |
Array
(
[id] => 18924550
[patent_doc_number] => 20240027554
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => METHOD AND SYSTEM FOR USING FITTED RELAXATION DATA TO IMPROVE A PRODUCT
[patent_app_type] => utility
[patent_app_number] => 18/224292
[patent_app_country] => US
[patent_app_date] => 2023-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224292
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/224292 | METHOD AND SYSTEM FOR USING FITTED RELAXATION DATA TO IMPROVE A PRODUCT | Jul 19, 2023 | Pending |
Array
(
[id] => 18904970
[patent_doc_number] => 20240020455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => SOFTWARE-DEFINED WAFER-LEVEL SWITCHING SYSTEM DESIGN METHOD AND APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/351464
[patent_app_country] => US
[patent_app_date] => 2023-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4875
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351464
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/351464 | Software-defined wafer-level switching system design method and apparatus | Jul 11, 2023 | Issued |
Array
(
[id] => 18727476
[patent_doc_number] => 20230341765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => METHOD AND SYSTEM FOR LAYOUT ENHANCEMENT BASED ON INTER-CELL CORRELATION
[patent_app_type] => utility
[patent_app_number] => 18/344844
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8481
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344844
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344844 | Method and system for layout enhancement based on inter-cell correlation | Jun 28, 2023 | Issued |
Array
(
[id] => 18713397
[patent_doc_number] => 20230336033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => TWO-SIDED INDUCTIVE CHARGING COIL
[patent_app_type] => utility
[patent_app_number] => 18/213656
[patent_app_country] => US
[patent_app_date] => 2023-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213656
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/213656 | Two-sided inductive charging coil | Jun 22, 2023 | Issued |
Array
(
[id] => 18866517
[patent_doc_number] => 20230420954
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => POWER SUPPLY CHARGING DEVICE, KIT, AND OPERATING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/212794
[patent_app_country] => US
[patent_app_date] => 2023-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18526
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212794
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/212794 | POWER SUPPLY CHARGING DEVICE, KIT, AND OPERATING METHOD | Jun 21, 2023 | Pending |
Array
(
[id] => 20304425
[patent_doc_number] => 12450418
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Semiconductor layout in FinFET technologies
[patent_app_type] => utility
[patent_app_number] => 18/337781
[patent_app_country] => US
[patent_app_date] => 2023-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3661
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337781
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/337781 | Semiconductor layout in FinFET technologies | Jun 19, 2023 | Issued |
Array
(
[id] => 19420145
[patent_doc_number] => 20240296268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-05
[patent_title] => METHODS OF SELECTING DEVICES IN CIRCUIT DESIGN
[patent_app_type] => utility
[patent_app_number] => 18/337262
[patent_app_country] => US
[patent_app_date] => 2023-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11843
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337262
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/337262 | METHODS OF SELECTING DEVICES IN CIRCUIT DESIGN | Jun 18, 2023 | Pending |
Array
(
[id] => 19645106
[patent_doc_number] => 20240419626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => PERFORMANCE EVALUATOR FOR A HETEROGENOUS HARDWARE PLATFORM
[patent_app_type] => utility
[patent_app_number] => 18/336777
[patent_app_country] => US
[patent_app_date] => 2023-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336777
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/336777 | PERFORMANCE EVALUATOR FOR A HETEROGENOUS HARDWARE PLATFORM | Jun 15, 2023 | Pending |
Array
(
[id] => 20610255
[patent_doc_number] => 12585857
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Method for automated standard cell design
[patent_app_type] => utility
[patent_app_number] => 18/333159
[patent_app_country] => US
[patent_app_date] => 2023-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 54
[patent_no_of_words] => 11210
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333159
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/333159 | Method for automated standard cell design | Jun 11, 2023 | Issued |
Array
(
[id] => 19053599
[patent_doc_number] => 20240095568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => Parametric Amplification in a Quantum Computing System
[patent_app_type] => utility
[patent_app_number] => 18/327918
[patent_app_country] => US
[patent_app_date] => 2023-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21180
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327918
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/327918 | Parametric Amplification in a Quantum Computing System | Jun 1, 2023 | Pending |
Array
(
[id] => 18660174
[patent_doc_number] => 20230306181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => LEAKAGE ANALYSIS ON SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/327557
[patent_app_country] => US
[patent_app_date] => 2023-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9845
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327557
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/327557 | LEAKAGE ANALYSIS ON SEMICONDUCTOR DEVICE | May 31, 2023 | Pending |
Array
(
[id] => 18954559
[patent_doc_number] => 20240042886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => VEHICLE, POWER ADJUSTMENT SYSTEM, AND POWER EQUIPMENT
[patent_app_type] => utility
[patent_app_number] => 18/326083
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6440
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326083
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/326083 | VEHICLE, POWER ADJUSTMENT SYSTEM, AND POWER EQUIPMENT | May 30, 2023 | Pending |