Search

Sean Mcgarry

Examiner (ID: 7001, Phone: (571)272-0761 , Office: P/1674 )

Most Active Art Unit
1635
Art Unit(s)
1809, 1674, 1624, 1635, 1621, 1805
Total Applications
1931
Issued Applications
1097
Pending Applications
308
Abandoned Applications
560

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17901599 [patent_doc_number] => 20220311261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => BATTERY MANAGEMENT SYSTEM AND BATTERY MANAGEMENT METHOD [patent_app_type] => utility [patent_app_number] => 17/695897 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695897 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695897
Battery management system and battery management method Mar 15, 2022 Issued
Array ( [id] => 17866320 [patent_doc_number] => 20220289055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => POSITIONING DEVICE FOR LOCATION POSITIONING OF ENERGY STORAGE CELLS [patent_app_type] => utility [patent_app_number] => 17/693347 [patent_app_country] => US [patent_app_date] => 2022-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693347
POSITIONING DEVICE FOR LOCATION POSITIONING OF ENERGY STORAGE CELLS Mar 11, 2022 Pending
Array ( [id] => 19917887 [patent_doc_number] => 12293257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Device with two superposed electrostatic control gate levels [patent_app_type] => utility [patent_app_number] => 17/654181 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 3360 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654181
Device with two superposed electrostatic control gate levels Mar 8, 2022 Issued
Array ( [id] => 18795911 [patent_doc_number] => 11829700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Method of analyzing and detecting critical cells [patent_app_type] => utility [patent_app_number] => 17/690990 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690990
Method of analyzing and detecting critical cells Mar 8, 2022 Issued
Array ( [id] => 19827960 [patent_doc_number] => 12248743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Cell architecture with backside power rails [patent_app_type] => utility [patent_app_number] => 17/685166 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685166
Cell architecture with backside power rails Mar 1, 2022 Issued
Array ( [id] => 19219509 [patent_doc_number] => 20240184213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METHOD OF PATTERN SELECTION FOR A SEMICONDUCTOR MANUFACTURING RELATED PROCESS [patent_app_type] => utility [patent_app_number] => 18/278881 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18278881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/278881
METHOD OF PATTERN SELECTION FOR A SEMICONDUCTOR MANUFACTURING RELATED PROCESS Feb 27, 2022 Pending
Array ( [id] => 17738704 [patent_doc_number] => 20220224166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => POWER TRANSMITTING APPARATUS, CONTROL METHOD FOR POWER TRANSMITTING APPARATUS, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/678880 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/678880
Power transmitting apparatus, control method for power transmitting apparatus, and storage medium Feb 22, 2022 Issued
Array ( [id] => 18365635 [patent_doc_number] => 20230147226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SIZE SETTING METHOD FOR POWER SWITCH TRANSISTOR AND SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/676882 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676882
Size setting method for power switch transistor and system thereof Feb 21, 2022 Issued
Array ( [id] => 19950313 [patent_doc_number] => 12321678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Integrated circuit with compact layout arrangement [patent_app_type] => utility [patent_app_number] => 17/673755 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1293 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673755
Integrated circuit with compact layout arrangement Feb 15, 2022 Issued
Array ( [id] => 18554204 [patent_doc_number] => 20230252217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => RULE CHECK HEATMAP PREDICTION [patent_app_type] => utility [patent_app_number] => 17/650656 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650656
Rule check heatmap prediction Feb 9, 2022 Issued
Array ( [id] => 17613412 [patent_doc_number] => 20220155692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => Optical Proximity Correction and Photomasks [patent_app_type] => utility [patent_app_number] => 17/665757 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665757
Optical proximity correction and photomasks Feb 6, 2022 Issued
Array ( [id] => 17812090 [patent_doc_number] => 20220263925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SYSTEM AND METHOD FOR SYNTHESIS OF CONNECTIVITY TO AN INTERCONNECT IN A MULTI-PROTOCOL SYSTEM-ON-CHIP (SoC) [patent_app_type] => utility [patent_app_number] => 17/665578 [patent_app_country] => US [patent_app_date] => 2022-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665578
System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC) Feb 5, 2022 Issued
Array ( [id] => 18555790 [patent_doc_number] => 20230253807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => Battery and Charging Case [patent_app_type] => utility [patent_app_number] => 17/665344 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665344
Battery and Charging Case Feb 3, 2022 Pending
Array ( [id] => 18668370 [patent_doc_number] => 11775269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Generating a synchronous digital circuit from a source code construct defining a function call [patent_app_type] => utility [patent_app_number] => 17/592489 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592489 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/592489
Generating a synchronous digital circuit from a source code construct defining a function call Feb 2, 2022 Issued
Array ( [id] => 20111850 [patent_doc_number] => 12362590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Controlling bulk capacitance charge in a power tool device [patent_app_type] => utility [patent_app_number] => 17/586496 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586496
Controlling bulk capacitance charge in a power tool device Jan 26, 2022 Issued
Array ( [id] => 19964999 [patent_doc_number] => 12334521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => System and method for reusing an electric vehicle battery [patent_app_type] => utility [patent_app_number] => 17/580294 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580294
System and method for reusing an electric vehicle battery Jan 19, 2022 Issued
Array ( [id] => 17916086 [patent_doc_number] => 20220318482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => COMPUTER-READABLE RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT DEVICE [patent_app_type] => utility [patent_app_number] => 17/580214 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580214
COMPUTER-READABLE RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT DEVICE Jan 19, 2022 Abandoned
Array ( [id] => 19906811 [patent_doc_number] => 12283832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Total voltage follow-up charging method and system [patent_app_type] => utility [patent_app_number] => 17/574596 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574596
Total voltage follow-up charging method and system Jan 12, 2022 Issued
Array ( [id] => 18007356 [patent_doc_number] => 20220366122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD OF DESIGNING INTERCONNECT STRUCTURE OF SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/572860 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572860
Method of designing interconnect structure of semiconductor apparatus and method of manufacturing semiconductor apparatus using the same Jan 10, 2022 Issued
Array ( [id] => 20081197 [patent_doc_number] => 12355278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Efficiency measuring apparatus, active equalizer inductor design tool and equalizer design app [patent_app_type] => utility [patent_app_number] => 17/646933 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 597 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646933
Efficiency measuring apparatus, active equalizer inductor design tool and equalizer design app Jan 3, 2022 Issued
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