Search

Selim U. Ahmed

Examiner (ID: 11248, Phone: (571)270-5025 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2896, 2826, CQIC, 4122
Total Applications
974
Issued Applications
852
Pending Applications
3
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11571842 [patent_doc_number] => 20170110487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'FORMING METHOD FOR STRUCTURE OF CROSSING DATALINES AND SCANNING LINES IN DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/395458 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3860 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395458 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395458
Forming method for structure of crossing datalines and scanning lines in display device Dec 29, 2016 Issued
Array ( [id] => 16642297 [patent_doc_number] => 10920138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Red phosphor and light emitting device [patent_app_type] => utility [patent_app_number] => 15/391828 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3907 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391828
Red phosphor and light emitting device Dec 26, 2016 Issued
Array ( [id] => 12436251 [patent_doc_number] => 09978600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Semiconductor electronic devices and methods of manufacture thereof [patent_app_type] => utility [patent_app_number] => 15/369159 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 95 [patent_no_of_words] => 10201 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/369159
Semiconductor electronic devices and methods of manufacture thereof Dec 4, 2016 Issued
Array ( [id] => 13921619 [patent_doc_number] => 10204934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Thin film transistor, array substrate, methods for fabricating the same, and display device [patent_app_type] => utility [patent_app_number] => 15/522811 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5242 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15522811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/522811
Thin film transistor, array substrate, methods for fabricating the same, and display device Oct 20, 2016 Issued
Array ( [id] => 11831885 [patent_doc_number] => 09728635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Uniform gate length in vertical field effect transistors' [patent_app_type] => utility [patent_app_number] => 15/292423 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3883 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292423
Uniform gate length in vertical field effect transistors Oct 12, 2016 Issued
Array ( [id] => 12045678 [patent_doc_number] => 09823271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Semiconductor testing structures and semiconductor testing apparatus' [patent_app_type] => utility [patent_app_number] => 15/280777 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280777 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/280777
Semiconductor testing structures and semiconductor testing apparatus Sep 28, 2016 Issued
Array ( [id] => 11883830 [patent_doc_number] => 09755014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth' [patent_app_type] => utility [patent_app_number] => 15/279192 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3259 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279192
Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth Sep 27, 2016 Issued
Array ( [id] => 15858349 [patent_doc_number] => 10644478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Light source module and method of manufacturing light source module [patent_app_type] => utility [patent_app_number] => 15/757525 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4488 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15757525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/757525
Light source module and method of manufacturing light source module Sep 11, 2016 Issued
Array ( [id] => 13271113 [patent_doc_number] => 10147643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Array substrate, manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 15/521079 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4030 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15521079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/521079
Array substrate, manufacturing method thereof, and display device Sep 6, 2016 Issued
Array ( [id] => 13392693 [patent_doc_number] => 20180247889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/757389 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15757389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/757389
Semiconductor device including external terminal groups Sep 1, 2016 Issued
Array ( [id] => 11495348 [patent_doc_number] => 20170069533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'Method for Fabricating Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/236427 [patent_app_country] => US [patent_app_date] => 2016-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236427
Method for fabricating semiconductor device including a via hole in a mask pattern Aug 12, 2016 Issued
Array ( [id] => 11432255 [patent_doc_number] => 09570582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method of removing dummy gate dielectric layer' [patent_app_type] => utility [patent_app_number] => 15/235208 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3172 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235208 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235208
Method of removing dummy gate dielectric layer Aug 11, 2016 Issued
Array ( [id] => 11974728 [patent_doc_number] => 20170278882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/236246 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236246 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236246
Image sensor and method for fabricating the same Aug 11, 2016 Issued
Array ( [id] => 11718143 [patent_doc_number] => 20170186642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/236173 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236173
Method for manufacturing isolation structure Aug 11, 2016 Issued
Array ( [id] => 11532762 [patent_doc_number] => 20170092742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'INSULATED GATE TYPE SWITCHING DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/235726 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8527 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235726
Insulated gate type switching device and method for manufacturing the same Aug 11, 2016 Issued
Array ( [id] => 12188892 [patent_doc_number] => 20180047828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHOD OF FORMING VERTICAL TRANSISTOR HAVING DUAL BOTTOM SPACERS' [patent_app_type] => utility [patent_app_number] => 15/235829 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235829
Method of forming vertical transistor having dual bottom spacers Aug 11, 2016 Issued
Array ( [id] => 11432235 [patent_doc_number] => 09570562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method of planarizing polysilicon gate' [patent_app_type] => utility [patent_app_number] => 15/235172 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2560 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235172
Method of planarizing polysilicon gate Aug 11, 2016 Issued
Array ( [id] => 11732775 [patent_doc_number] => 20170194219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'ARRAY SUBSTRATE, ITS MANUFACTURING METHOD AND TESTING METHOD, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/235945 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235945
Array substrate, its manufacturing method and testing method, and display device Aug 11, 2016 Issued
Array ( [id] => 11740153 [patent_doc_number] => 09704746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask' [patent_app_type] => utility [patent_app_number] => 15/235892 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235892
Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask Aug 11, 2016 Issued
Array ( [id] => 12102064 [patent_doc_number] => 09859163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Methods for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/235175 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235175 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235175
Methods for manufacturing a semiconductor device Aug 11, 2016 Issued
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