Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3595973
[patent_doc_number] => 05581743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'CKD to fixed block mapping for optimum performance and space utilization'
[patent_app_type] => 1
[patent_app_number] => 8/411068
[patent_app_country] => US
[patent_app_date] => 1995-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4381
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581743.pdf
[firstpage_image] =>[orig_patent_app_number] => 411068
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/411068 | CKD to fixed block mapping for optimum performance and space utilization | Mar 26, 1995 | Issued |
Array
(
[id] => 3701209
[patent_doc_number] => 05692153
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Method and system for verifying execution order within a multiprocessor data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/405058
[patent_app_country] => US
[patent_app_date] => 1995-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4168
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/692/05692153.pdf
[firstpage_image] =>[orig_patent_app_number] => 405058
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/405058 | Method and system for verifying execution order within a multiprocessor data processing system | Mar 15, 1995 | Issued |
Array
(
[id] => 3700775
[patent_doc_number] => 05696958
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline'
[patent_app_type] => 1
[patent_app_number] => 8/405622
[patent_app_country] => US
[patent_app_date] => 1995-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 14143
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696958.pdf
[firstpage_image] =>[orig_patent_app_number] => 405622
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/405622 | Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline | Mar 14, 1995 | Issued |
08/398923 | UNIVERSAL SOFTWARE KEY PROCESS | Mar 5, 1995 | Abandoned |
Array
(
[id] => 3621628
[patent_doc_number] => 05590328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Protocol parallel processing apparatus having a plurality of CPUs allocated to process hierarchical protocols'
[patent_app_type] => 1
[patent_app_number] => 8/399331
[patent_app_country] => US
[patent_app_date] => 1995-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3878
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/590/05590328.pdf
[firstpage_image] =>[orig_patent_app_number] => 399331
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/399331 | Protocol parallel processing apparatus having a plurality of CPUs allocated to process hierarchical protocols | Mar 5, 1995 | Issued |
08/396590 | METHOD OF PERFORMING A COMPILATION PROCESS FOR DETERMINING A BRANCH PROBABILITY AND AN APPARATUS FOR PERFORMING THE COMPILATION PROCESS | Feb 28, 1995 | Abandoned |
Array
(
[id] => 3604476
[patent_doc_number] => 05568623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method for rearranging instruction sequence in risc architecture'
[patent_app_type] => 1
[patent_app_number] => 8/387393
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 1891
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568623.pdf
[firstpage_image] =>[orig_patent_app_number] => 387393
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387393 | Method for rearranging instruction sequence in risc architecture | Feb 12, 1995 | Issued |
08/386976 | METHOD AND SYSTEM FOR EFFICIENTLY FETCHING FROM CACHE DURING A CACHE FILL OPERATION | Feb 9, 1995 | Abandoned |
08/377128 | NETWORK SYSTEM WITH RESILIENT VIRTUAL FAULT TOLERANT SESSIONS | Jan 22, 1995 | Abandoned |
08/373512 | SYSTEM FOR RECREATING A PRINTED CIRCUIT BOARD FROM DISJOINTLY FORMATTED DATA | Jan 11, 1995 | Abandoned |
Array
(
[id] => 3707973
[patent_doc_number] => 05596743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Field programmable logic device with dynamic interconnections to a dynamic logic core'
[patent_app_type] => 1
[patent_app_number] => 8/369291
[patent_app_country] => US
[patent_app_date] => 1995-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 8230
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/596/05596743.pdf
[firstpage_image] =>[orig_patent_app_number] => 369291
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/369291 | Field programmable logic device with dynamic interconnections to a dynamic logic core | Jan 5, 1995 | Issued |
Array
(
[id] => 4201804
[patent_doc_number] => 06094670
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Method of extracting and editing message blocks in telecommunications management network and arrangement thereof'
[patent_app_type] => 1
[patent_app_number] => 8/367930
[patent_app_country] => US
[patent_app_date] => 1995-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2780
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094670.pdf
[firstpage_image] =>[orig_patent_app_number] => 367930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/367930 | Method of extracting and editing message blocks in telecommunications management network and arrangement thereof | Jan 2, 1995 | Issued |
Array
(
[id] => 3540102
[patent_doc_number] => 05542059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order'
[patent_app_type] => 1
[patent_app_number] => 8/361017
[patent_app_country] => US
[patent_app_date] => 1994-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6000
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/542/05542059.pdf
[firstpage_image] =>[orig_patent_app_number] => 361017
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/361017 | Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order | Dec 20, 1994 | Issued |
Array
(
[id] => 3540278
[patent_doc_number] => 05542070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Method for rapid development of software systems'
[patent_app_type] => 1
[patent_app_number] => 8/358651
[patent_app_country] => US
[patent_app_date] => 1994-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 13678
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/542/05542070.pdf
[firstpage_image] =>[orig_patent_app_number] => 358651
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/358651 | Method for rapid development of software systems | Dec 18, 1994 | Issued |
Array
(
[id] => 3783308
[patent_doc_number] => 05850573
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Control method for peripheral device in host computer connectable to a plurality of peripheral devices'
[patent_app_type] => 1
[patent_app_number] => 8/345334
[patent_app_country] => US
[patent_app_date] => 1994-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 6009
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850573.pdf
[firstpage_image] =>[orig_patent_app_number] => 345334
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/345334 | Control method for peripheral device in host computer connectable to a plurality of peripheral devices | Nov 20, 1994 | Issued |
08/340224 | METHOD AND APPARATUS FOR MONITORING AND MANAGING OPERATIONAL CHARATEISTICS OF WORKSTATIONS ON A NETWORK WITHOUT USER NETWORK IMPACT | Nov 15, 1994 | Abandoned |
Array
(
[id] => 3829221
[patent_doc_number] => 05771396
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Merging serial I/O data and digitized audio data on a serial computer bus'
[patent_app_type] => 1
[patent_app_number] => 8/341284
[patent_app_country] => US
[patent_app_date] => 1994-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3225
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/771/05771396.pdf
[firstpage_image] =>[orig_patent_app_number] => 341284
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/341284 | Merging serial I/O data and digitized audio data on a serial computer bus | Nov 15, 1994 | Issued |
Array
(
[id] => 3518651
[patent_doc_number] => 05515520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Data processing system for single-precision and double-precision data'
[patent_app_type] => 1
[patent_app_number] => 8/337411
[patent_app_country] => US
[patent_app_date] => 1994-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 3809
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/515/05515520.pdf
[firstpage_image] =>[orig_patent_app_number] => 337411
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/337411 | Data processing system for single-precision and double-precision data | Nov 6, 1994 | Issued |
Array
(
[id] => 3474098
[patent_doc_number] => 05469545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Expandable communication system with data flow control'
[patent_app_type] => 1
[patent_app_number] => 8/335557
[patent_app_country] => US
[patent_app_date] => 1994-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 27688
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 1064
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469545.pdf
[firstpage_image] =>[orig_patent_app_number] => 335557
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/335557 | Expandable communication system with data flow control | Nov 6, 1994 | Issued |
Array
(
[id] => 3474098
[patent_doc_number] => 05469545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Expandable communication system with data flow control'
[patent_app_type] => 1
[patent_app_number] => 8/335557
[patent_app_country] => US
[patent_app_date] => 1994-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 27688
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 1064
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469545.pdf
[firstpage_image] =>[orig_patent_app_number] => 335557
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/335557 | Expandable communication system with data flow control | Nov 6, 1994 | Issued |