Search

Selim U Ahmed

Examiner (ID: 14822, Phone: (571)270-5025 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, CQIC, 4122, 2826, 2896
Total Applications
974
Issued Applications
848
Pending Applications
3
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3474098 [patent_doc_number] => 05469545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Expandable communication system with data flow control' [patent_app_type] => 1 [patent_app_number] => 8/335557 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 27688 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1064 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469545.pdf [firstpage_image] =>[orig_patent_app_number] => 335557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335557
Expandable communication system with data flow control Nov 6, 1994 Issued
Array ( [id] => 3474098 [patent_doc_number] => 05469545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Expandable communication system with data flow control' [patent_app_type] => 1 [patent_app_number] => 8/335557 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 27688 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1064 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469545.pdf [firstpage_image] =>[orig_patent_app_number] => 335557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335557
Expandable communication system with data flow control Nov 6, 1994 Issued
Array ( [id] => 3616690 [patent_doc_number] => 05579511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Method and apparatus for checking the integrity of a complex computer installation used in the flight control of an aircraft' [patent_app_type] => 1 [patent_app_number] => 8/324374 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4635 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579511.pdf [firstpage_image] =>[orig_patent_app_number] => 324374 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324374
Method and apparatus for checking the integrity of a complex computer installation used in the flight control of an aircraft Oct 16, 1994 Issued
Array ( [id] => 3576101 [patent_doc_number] => 05526523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Interface between operating system and operating system extension' [patent_app_type] => 1 [patent_app_number] => 8/315855 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3401 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526523.pdf [firstpage_image] =>[orig_patent_app_number] => 315855 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315855
Interface between operating system and operating system extension Sep 29, 1994 Issued
Array ( [id] => 3505475 [patent_doc_number] => 05537561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Processor' [patent_app_type] => 1 [patent_app_number] => 8/315505 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 39 [patent_no_of_words] => 7571 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 560 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537561.pdf [firstpage_image] =>[orig_patent_app_number] => 315505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315505
Processor Sep 29, 1994 Issued
08/310202 METHOD AND APPARATUS FOR CONFIGURING MEMORY CIRCUITS Sep 20, 1994 Abandoned
Array ( [id] => 4257813 [patent_doc_number] => 06145072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same' [patent_app_type] => 1 [patent_app_number] => 8/309565 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4802 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145072.pdf [firstpage_image] =>[orig_patent_app_number] => 309565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/309565
Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same Sep 19, 1994 Issued
08/305507 MULTIPLE EXECUTION UNIT DISPATCH WITH INSTRUCTION SHIFTING BETWEEN FIRST AND SECOND INSTRUCTION BUFFERS BASED UPON DATA DEPENDENCY Sep 12, 1994 Abandoned
Array ( [id] => 3694283 [patent_doc_number] => 05634018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Presentation supporting method and apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 8/304209 [patent_app_country] => US [patent_app_date] => 1994-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 11419 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634018.pdf [firstpage_image] =>[orig_patent_app_number] => 304209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/304209
Presentation supporting method and apparatus therefor Sep 11, 1994 Issued
08/301836 PIPELINE INSTRUCTION BOX INCLUDING INSTRUCTION SCHEDULE AND REGISTER MAPPER FOR PIPELINE PROCESSOR Sep 6, 1994 Abandoned
Array ( [id] => 1480824 [patent_doc_number] => 06389481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Automatic program documentation' [patent_app_type] => B1 [patent_app_number] => 08/301833 [patent_app_country] => US [patent_app_date] => 1994-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 4513 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389481.pdf [firstpage_image] =>[orig_patent_app_number] => 08301833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/301833
Automatic program documentation Sep 5, 1994 Issued
Array ( [id] => 4387603 [patent_doc_number] => 06275864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Matrix switch for a network management system' [patent_app_type] => 1 [patent_app_number] => 8/294882 [patent_app_country] => US [patent_app_date] => 1994-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 23274 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275864.pdf [firstpage_image] =>[orig_patent_app_number] => 294882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/294882
Matrix switch for a network management system Aug 22, 1994 Issued
08/287715 METHOD FOR DECODING SEQUENCES OF GUEST INSTRUCTIONS FOR A HOST COMPUTER Aug 8, 1994 Abandoned
Array ( [id] => 3553514 [patent_doc_number] => 05481748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Method and apparatus for reducing the processing time required to solve numerical problems' [patent_app_type] => 1 [patent_app_number] => 8/286918 [patent_app_country] => US [patent_app_date] => 1994-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 14487 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481748.pdf [firstpage_image] =>[orig_patent_app_number] => 286918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/286918
Method and apparatus for reducing the processing time required to solve numerical problems Aug 7, 1994 Issued
Array ( [id] => 3626327 [patent_doc_number] => 05511174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths' [patent_app_type] => 1 [patent_app_number] => 8/286662 [patent_app_country] => US [patent_app_date] => 1994-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1345 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 425 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511174.pdf [firstpage_image] =>[orig_patent_app_number] => 286662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/286662
Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths Aug 4, 1994 Issued
Array ( [id] => 3494993 [patent_doc_number] => 05446852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Method of reducing noise signals caused by fluctuations in power requirements of digital signal processor having recurring wait routines' [patent_app_type] => 1 [patent_app_number] => 8/283926 [patent_app_country] => US [patent_app_date] => 1994-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2940 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446852.pdf [firstpage_image] =>[orig_patent_app_number] => 283926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283926
Method of reducing noise signals caused by fluctuations in power requirements of digital signal processor having recurring wait routines Jul 31, 1994 Issued
08/279921 A SYSTEM FOR EVALUATING THE RESULTS OF LOGIC SIMULATION Jul 24, 1994 Abandoned
Array ( [id] => 4374578 [patent_doc_number] => 06219627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Architecture of a chip having multiple processors and multiple memories' [patent_app_type] => 1 [patent_app_number] => 8/274132 [patent_app_country] => US [patent_app_date] => 1994-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2884 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219627.pdf [firstpage_image] =>[orig_patent_app_number] => 274132 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/274132
Architecture of a chip having multiple processors and multiple memories Jul 11, 1994 Issued
08/272635 COMMUNICATION SYSTEM SIGNAL PROCESSING APPARATUS WITH ROM STORED SIGNAL PROCEDURES EXECUTED IN RAM Jul 10, 1994 Abandoned
08/268494 METHOD AND SYSTEM DISTRIBUTING ASYNCHRONOUS INPUT FROM A SYSTEM INPUT QUEUE TO REDUCE CONTEXT SWITCHES Jun 29, 1994 Abandoned
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