Search

Selim U. Ahmed

Examiner (ID: 16707)

Most Active Art Unit
2816
Art Unit(s)
2816, 2896, CQIC, 4122, 2826
Total Applications
974
Issued Applications
852
Pending Applications
3
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15939083 [patent_doc_number] => 20200161175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => TOP VIA BACK END OF THE LINE INTERCONNECT INTEGRATION [patent_app_type] => utility [patent_app_number] => 16/194545 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194545
Top via back end of the line interconnect integration Nov 18, 2018 Issued
Array ( [id] => 15939163 [patent_doc_number] => 20200161215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => INTEGRATED HEAT SPREADER WITH CONFIGURABLE HEAT FINS [patent_app_type] => utility [patent_app_number] => 16/194560 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194560
Integrated heat spreader with configurable heat fins Nov 18, 2018 Issued
Array ( [id] => 14542589 [patent_doc_number] => 20190206916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => CHIP SCALE PACKAGE STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/194802 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194802
Chip scale package structures Nov 18, 2018 Issued
Array ( [id] => 16593876 [patent_doc_number] => 10903153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Thinned die stack [patent_app_type] => utility [patent_app_number] => 16/194377 [patent_app_country] => US [patent_app_date] => 2018-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9198 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194377
Thinned die stack Nov 17, 2018 Issued
Array ( [id] => 15717737 [patent_doc_number] => 20200105636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => CHIP PACKAGE STRUCTURE HAVING FUNCTION OF PREVENTING ADHESIVE FROM OVERFLOWING [patent_app_type] => utility [patent_app_number] => 16/194316 [patent_app_country] => US [patent_app_date] => 2018-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194316
CHIP PACKAGE STRUCTURE HAVING FUNCTION OF PREVENTING ADHESIVE FROM OVERFLOWING Nov 16, 2018 Abandoned
Array ( [id] => 16372662 [patent_doc_number] => 10804428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => High efficiency light emitting diode (LED) with low injection current [patent_app_type] => utility [patent_app_number] => 16/194177 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7418 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194177
High efficiency light emitting diode (LED) with low injection current Nov 15, 2018 Issued
Array ( [id] => 16536544 [patent_doc_number] => 10879157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => High density substrate and stacked silicon package assembly having the same [patent_app_type] => utility [patent_app_number] => 16/194213 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194213 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194213
High density substrate and stacked silicon package assembly having the same Nov 15, 2018 Issued
Array ( [id] => 14350647 [patent_doc_number] => 20190157296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => REVERSE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/194225 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194225
Reverse memory cell Nov 15, 2018 Issued
Array ( [id] => 16332478 [patent_doc_number] => 20200303444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => IMAGING DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/763024 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16763024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/763024
Imaging device and electronic device Nov 12, 2018 Issued
Array ( [id] => 14475963 [patent_doc_number] => 20190189630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => Methods of Filling Openings with Conductive Material, and Assemblies Having Vertically-Stacked Conductive Structures [patent_app_type] => utility [patent_app_number] => 16/186042 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186042
Methods of filling openings with conductive material, and assemblies having vertically-stacked conductive structures Nov 8, 2018 Issued
Array ( [id] => 14049789 [patent_doc_number] => 20190081002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR PACKAGES WITH EMBEDDED BRIDGE INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/184726 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184726
Semiconductor packages with embedded bridge interconnects Nov 7, 2018 Issued
Array ( [id] => 14526221 [patent_doc_number] => 10340381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method for fabricating semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/180033 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180033
Method for fabricating semiconductor structure Nov 4, 2018 Issued
Array ( [id] => 15061553 [patent_doc_number] => 10461089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Cell boundary structure for embedded memory [patent_app_type] => utility [patent_app_number] => 16/167879 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 16450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167879 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167879
Cell boundary structure for embedded memory Oct 22, 2018 Issued
Array ( [id] => 13909423 [patent_doc_number] => 20190043916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MICRO LED DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/154939 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154939
Micro LED display device and method of fabricating the same Oct 8, 2018 Issued
Array ( [id] => 15108977 [patent_doc_number] => 10475820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Peeling method, display device, module, and electronic device [patent_app_type] => utility [patent_app_number] => 16/143970 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 118 [patent_no_of_words] => 25633 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143970
Peeling method, display device, module, and electronic device Sep 26, 2018 Issued
Array ( [id] => 15955297 [patent_doc_number] => 10665564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => On-bonder automatic overhang die optimization tool for wire bonding and related methods [patent_app_type] => utility [patent_app_number] => 16/142662 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142662
On-bonder automatic overhang die optimization tool for wire bonding and related methods Sep 25, 2018 Issued
Array ( [id] => 15687857 [patent_doc_number] => 20200098592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => CONTROLLING OF HEIGHT OF HIGH-DENSITY INTERCONNECTION STRUCTURE ON SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/141153 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141153
Controlling of height of high-density interconnection structure on substrate Sep 24, 2018 Issued
Array ( [id] => 15791515 [patent_doc_number] => 10629489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices [patent_app_type] => utility [patent_app_number] => 16/139932 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139932
Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices Sep 23, 2018 Issued
Array ( [id] => 14285667 [patent_doc_number] => 20190140118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => Multi-Element Alloy Compound, Ink and Film Absorption Layer Thereof, and Methods for Preparing the Same [patent_app_type] => utility [patent_app_number] => 16/137941 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137941
Multi-Element Alloy Compound, Ink and Film Absorption Layer Thereof, and Methods for Preparing the Same Sep 20, 2018 Abandoned
Array ( [id] => 13848225 [patent_doc_number] => 20190027597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => SEMICONDUCTOR DEVICE FOR POWER TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/137279 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137279 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137279
Semiconductor device for power transistor Sep 19, 2018 Issued
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