Search

Selim U. Ahmed

Examiner (ID: 11248, Phone: (571)270-5025 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2896, 2826, CQIC, 4122
Total Applications
974
Issued Applications
852
Pending Applications
3
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13405289 [patent_doc_number] => 20180254187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => CHARGE-TRAP LAYER SEPARATION AND WORD-LINE ISOLATION IN A 3-D NAND STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/966787 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966787 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966787
Charge-trap layer separation and word-line isolation in a 3-D NAND structure Apr 29, 2018 Issued
Array ( [id] => 13363513 [patent_doc_number] => 20180233296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => Perovskite Thin Film Low-pressure Chemical Deposition Equipment and Uses Thereof [patent_app_type] => utility [patent_app_number] => 15/944694 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944694 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944694
Perovskite thin film low-pressure chemical deposition equipment and uses thereof Apr 2, 2018 Issued
Array ( [id] => 14644703 [patent_doc_number] => 10367102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Electronic component and equipment [patent_app_type] => utility [patent_app_number] => 15/910882 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 36 [patent_no_of_words] => 8350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910882
Electronic component and equipment Mar 1, 2018 Issued
Array ( [id] => 14573515 [patent_doc_number] => 20190214365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => HBM SILICON PHOTONIC TSV ARCHITECTURE FOR LOOKUP COMPUTING AI ACCELERATOR [patent_app_type] => utility [patent_app_number] => 15/911063 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911063
HBM silicon photonic TSV architecture for lookup computing AI accelerator Mar 1, 2018 Issued
Array ( [id] => 13420353 [patent_doc_number] => 20180261719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR DEVICE HAVING AN INTERNAL-FIELD-GUARDED ACTIVE REGION [patent_app_type] => utility [patent_app_number] => 15/910386 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910386
Semiconductor device having an internal-field-guarded active region Mar 1, 2018 Issued
Array ( [id] => 15170299 [patent_doc_number] => 10490655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Insulated gate bipolar transistor (IGBT) with high avalanche withstand [patent_app_type] => utility [patent_app_number] => 15/910384 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4273 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910384 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910384
Insulated gate bipolar transistor (IGBT) with high avalanche withstand Mar 1, 2018 Issued
Array ( [id] => 16230397 [patent_doc_number] => 10737934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => MEMS with over-voltage protection [patent_app_type] => utility [patent_app_number] => 15/911045 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911045 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911045
MEMS with over-voltage protection Mar 1, 2018 Issued
Array ( [id] => 13543643 [patent_doc_number] => 20180323368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/910427 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910427
Electronic device including an under layer and a perpendicular magnetic anisotropy increasing layer having a different crystal structure from the under layer Mar 1, 2018 Issued
Array ( [id] => 14916047 [patent_doc_number] => 10429340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Gas sensor [patent_app_type] => utility [patent_app_number] => 15/910892 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 70 [patent_no_of_words] => 19114 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910892
Gas sensor Mar 1, 2018 Issued
Array ( [id] => 13132285 [patent_doc_number] => 10084082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-25 [patent_title] => Bottom contact resistance reduction on VFET [patent_app_type] => utility [patent_app_number] => 15/905885 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/905885
Bottom contact resistance reduction on VFET Feb 26, 2018 Issued
Array ( [id] => 13229179 [patent_doc_number] => 10128372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => Bottom contact resistance reduction on VFET [patent_app_type] => utility [patent_app_number] => 15/905891 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905891 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/905891
Bottom contact resistance reduction on VFET Feb 26, 2018 Issued
Array ( [id] => 12896857 [patent_doc_number] => 20180190794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => METHOD OF FORMING VERTICAL TRANSISTOR HAVING DUAL BOTTOM SPACERS [patent_app_type] => utility [patent_app_number] => 15/897706 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897706
Method of forming vertical transistor having dual bottom spacers Feb 14, 2018 Issued
Array ( [id] => 13514579 [patent_doc_number] => 20180308832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => MICRO LED DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/889002 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889002
Micro LED display device and method of fabricating the same Feb 4, 2018 Issued
Array ( [id] => 13378407 [patent_doc_number] => 20180240745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/887780 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887780
Embedded trace substrate structure and semiconductor package structure including the same Feb 1, 2018 Issued
Array ( [id] => 16241647 [patent_doc_number] => 20200258881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => VERTICAL DIODE IN STACKED TRANSISTOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/649712 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649712 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649712
Vertical diode in stacked transistor architecture Jan 17, 2018 Issued
Array ( [id] => 14191273 [patent_doc_number] => 20190115342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => HIGH QUALITY FACTOR FIN METAL OXIDE SEMICONDUCTOR VARACTOR WITH IMPROVED NUMBER OF FINS [patent_app_type] => utility [patent_app_number] => 15/862533 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862533 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862533
HIGH QUALITY FACTOR FIN METAL OXIDE SEMICONDUCTOR VARACTOR WITH IMPROVED NUMBER OF FINS Jan 3, 2018 Abandoned
Array ( [id] => 12918385 [patent_doc_number] => 20180197971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/862569 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862569
Semiconductor structure and fabrication method thereof Jan 3, 2018 Issued
Array ( [id] => 15286793 [patent_doc_number] => 10516068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Thallium bromide (TIBr) semiconductors and devices with extended life apparatus, methods, and system [patent_app_type] => utility [patent_app_number] => 15/862307 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862307
Thallium bromide (TIBr) semiconductors and devices with extended life apparatus, methods, and system Jan 3, 2018 Issued
Array ( [id] => 14616783 [patent_doc_number] => 10361098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => QFN pin routing thru lead frame etching [patent_app_type] => utility [patent_app_number] => 15/848336 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3416 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848336 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848336
QFN pin routing thru lead frame etching Dec 19, 2017 Issued
Array ( [id] => 12917902 [patent_doc_number] => 20180197810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => LEAD FRAME AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/848550 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848550
Lead frame and method of manufacturing the same Dec 19, 2017 Issued
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