Search

Seong-ah A. Shin

Examiner (ID: 19172, Phone: (571)272-5933 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2659, 2658
Total Applications
475
Issued Applications
347
Pending Applications
50
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20274660 [patent_doc_number] => 12444444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Multi-write read-only memory array [patent_app_type] => utility [patent_app_number] => 18/529115 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3549 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529115
Multi-write read-only memory array Dec 4, 2023 Issued
Array ( [id] => 20044585 [patent_doc_number] => 20250182807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => REFRESH OPERATIONS IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) [patent_app_type] => utility [patent_app_number] => 18/529175 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529175
Refresh operations in embedded dynamic random access memories (DRAMs) Dec 4, 2023 Issued
Array ( [id] => 20305207 [patent_doc_number] => 12451203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Memory device and method of operating the memory device [patent_app_type] => utility [patent_app_number] => 18/521063 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7662 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521063
Memory device and method of operating the memory device Nov 27, 2023 Issued
Array ( [id] => 20036051 [patent_doc_number] => 20250174273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/519156 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519156
Integrated circuit structure and method for operating the same Nov 26, 2023 Issued
Array ( [id] => 19757820 [patent_doc_number] => 20250046385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MEMORY CONFIGURED TO PERFORM A CHANNEL PRECHARGE OPERATION AND METHOD OF OPERATING THE MEMORY [patent_app_type] => utility [patent_app_number] => 18/515975 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515975
Memory configured to perform a channel precharge operation and method of operating the memory Nov 20, 2023 Issued
Array ( [id] => 19610780 [patent_doc_number] => 12159660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Methods for row hammer mitigation and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 18/513319 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513319
Methods for row hammer mitigation and memory devices and systems employing the same Nov 16, 2023 Issued
Array ( [id] => 20019318 [patent_doc_number] => 20250157540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => VARIABLE FOGGY VERIFY LEVELS FOR SELECTED CHECKPOINT STATES FOR NON-VOLATILE MEMORY APPARATUSES [patent_app_type] => utility [patent_app_number] => 18/509708 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509708
Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses Nov 14, 2023 Issued
Array ( [id] => 20002096 [patent_doc_number] => 20250140318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SUB-BLOCK SEPARATION IN NAND MEMORY THROUGH WORD LINE BASED SELECTORS [patent_app_type] => utility [patent_app_number] => 18/499797 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499797 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499797
Sub-block separation in NAND memory through word line based selectors Oct 31, 2023 Issued
Array ( [id] => 19191158 [patent_doc_number] => 20240170071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SINGLE-LEVEL CELL PROGRAMMING WITH ADAPTIVE WORDLINE RAMP RATE [patent_app_type] => utility [patent_app_number] => 18/496660 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/496660
Single-level cell programming with adaptive wordline ramp rate Oct 26, 2023 Issued
Array ( [id] => 19646249 [patent_doc_number] => 20240420769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY DEVICE PERMITTING OVERWRITE PROGRAM OPERATION AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/494769 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494769
Memory device permitting overwrite program operation and operation method thereof Oct 25, 2023 Issued
Array ( [id] => 19749204 [patent_doc_number] => 20250037769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY, OPERATION METHODS THEREOF AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/491452 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491452
Memory, operation methods thereof and memory systems Oct 19, 2023 Issued
Array ( [id] => 18959021 [patent_doc_number] => 20240047348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ELECTRICAL FUSE BIT CELL IN INTEGRATED CIRCUIT HAVING BACKSIDE CONDUCTING LINES [patent_app_type] => utility [patent_app_number] => 18/489674 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489674
Electrical fuse bit cell in integrated circuit having backside conducting lines Oct 17, 2023 Issued
Array ( [id] => 19574875 [patent_doc_number] => 20240379167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/489394 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489394 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489394
MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE Oct 17, 2023 Issued
Array ( [id] => 19376444 [patent_doc_number] => 12068022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Integrated circuit and memory device including sampling circuit [patent_app_type] => utility [patent_app_number] => 18/488040 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488040
Integrated circuit and memory device including sampling circuit Oct 16, 2023 Issued
Array ( [id] => 18926781 [patent_doc_number] => 20240029785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTRATE AND PACKAGE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/479330 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479330 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479330
Techniques to couple high bandwidth memory device on silicon substrate and package substrate Oct 1, 2023 Issued
Array ( [id] => 19085936 [patent_doc_number] => 20240112737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => METHOD OF PROGRAMMING FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 18/477456 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/477456
Method of programming flash memory Sep 27, 2023 Issued
Array ( [id] => 20215975 [patent_doc_number] => 12412629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Memory device and operating method for memory device [patent_app_type] => utility [patent_app_number] => 18/474619 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474619
Memory device and operating method for memory device Sep 25, 2023 Issued
Array ( [id] => 19376462 [patent_doc_number] => 12068040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage [patent_app_type] => utility [patent_app_number] => 18/467793 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 10970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/467793
Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage Sep 14, 2023 Issued
Array ( [id] => 19328612 [patent_doc_number] => 12046301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 18/468078 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 10978 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/468078
Semiconductor integrated circuit Sep 14, 2023 Issued
Array ( [id] => 19054427 [patent_doc_number] => 20240096396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY DEVICE AND PRECHARGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/368446 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/368446
Memory device and precharging method thereof Sep 13, 2023 Issued
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