Search

Seong-ah A. Shin

Examiner (ID: 19172, Phone: (571)272-5933 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2659, 2658
Total Applications
475
Issued Applications
347
Pending Applications
50
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18848483 [patent_doc_number] => 20230410887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MEMORY ARRAY CONNECTIONS [patent_app_type] => utility [patent_app_number] => 18/182696 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182696
Memory array connections Mar 12, 2023 Issued
Array ( [id] => 19765715 [patent_doc_number] => 12224013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/183008 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 15123 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/183008
Semiconductor memory device Mar 12, 2023 Issued
Array ( [id] => 18958667 [patent_doc_number] => 20240046994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SERIAL-GATE TRANSISTOR AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/120244 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120244
Serial-gate transistor and nonvolatile memory device including the same Mar 9, 2023 Issued
Array ( [id] => 19054429 [patent_doc_number] => 20240096398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY DEVICE AND PRECHARGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/118235 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118235 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/118235
Memory device and precharging method thereof Mar 6, 2023 Issued
Array ( [id] => 18865584 [patent_doc_number] => 20230420021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/180021 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180021
Memory device and memory system Mar 6, 2023 Issued
Array ( [id] => 19740986 [patent_doc_number] => 12217825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Drive circuit and memory device [patent_app_type] => utility [patent_app_number] => 18/180038 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7259 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180038 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180038
Drive circuit and memory device Mar 6, 2023 Issued
Array ( [id] => 20161163 [patent_doc_number] => 12387796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory assembly with body biasing and related methods [patent_app_type] => utility [patent_app_number] => 18/178926 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178926
Memory assembly with body biasing and related methods Mar 5, 2023 Issued
Array ( [id] => 20647216 [patent_doc_number] => 12602159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Apparatus having segmented data lines and methods of their operation [patent_app_type] => utility [patent_app_number] => 18/117553 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6482 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117553 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/117553
Apparatus having segmented data lines and methods of their operation Mar 5, 2023 Issued
Array ( [id] => 18990857 [patent_doc_number] => 20240062826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/177730 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177730
Semiconductor storage device Mar 1, 2023 Issued
Array ( [id] => 18766748 [patent_doc_number] => 11817155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage [patent_app_type] => utility [patent_app_number] => 18/173211 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 10960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/173211
Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage Feb 22, 2023 Issued
Array ( [id] => 18998895 [patent_doc_number] => 11915748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Semiconductor memory device, memory system, and write method [patent_app_type] => utility [patent_app_number] => 18/112507 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 70 [patent_no_of_words] => 39772 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18112507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/112507
Semiconductor memory device, memory system, and write method Feb 21, 2023 Issued
Array ( [id] => 19384344 [patent_doc_number] => 20240274214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHOD [patent_app_type] => utility [patent_app_number] => 18/168628 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168628
Memory interface circuitry and built-in self-testing method Feb 13, 2023 Issued
Array ( [id] => 19252474 [patent_doc_number] => 20240203471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => LAYOUT PATTERN OF MAGNETORESISTIVE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/108025 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108025 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/108025
Layout pattern of magnetoresistive random access memory Feb 9, 2023 Issued
Array ( [id] => 19363921 [patent_doc_number] => 20240265955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => ELECTRONIC DEVICE, MEMORY DEVICE, AND WRITE LEVELING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/164570 [patent_app_country] => US [patent_app_date] => 2023-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164570
Electronic device, memory device, and write leveling method thereof Feb 3, 2023 Issued
Array ( [id] => 19610792 [patent_doc_number] => 12159672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Hybrid IMS CAM cell, memory device and data search method [patent_app_type] => utility [patent_app_number] => 18/162728 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 15831 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162728 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162728
Hybrid IMS CAM cell, memory device and data search method Jan 31, 2023 Issued
Array ( [id] => 18669714 [patent_doc_number] => 11776624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory system and memory device [patent_app_type] => utility [patent_app_number] => 18/159123 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 75 [patent_no_of_words] => 43503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/159123
Memory system and memory device Jan 24, 2023 Issued
Array ( [id] => 19626836 [patent_doc_number] => 12165683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Magnetic memory devices [patent_app_type] => utility [patent_app_number] => 18/096161 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096161
Magnetic memory devices Jan 11, 2023 Issued
Array ( [id] => 19507607 [patent_doc_number] => 12119036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Magnetic memory devices and methods of controlling domain sizes thereof [patent_app_type] => utility [patent_app_number] => 18/096089 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096089
Magnetic memory devices and methods of controlling domain sizes thereof Jan 11, 2023 Issued
Array ( [id] => 18669709 [patent_doc_number] => 11776619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Techniques to couple high bandwidth memory device on silicon substrate and package substrate [patent_app_type] => utility [patent_app_number] => 18/153183 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 13 [patent_no_of_words] => 9890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153183
Techniques to couple high bandwidth memory device on silicon substrate and package substrate Jan 10, 2023 Issued
Array ( [id] => 18394581 [patent_doc_number] => 20230162802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => FEEDBACK FOR POWER MANAGEMENT OF A MEMORY DIE USING CAPACITIVE COUPLING [patent_app_type] => utility [patent_app_number] => 18/094698 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094698 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094698
Feedback for power management of a memory die using capacitive coupling Jan 8, 2023 Issued
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