Search

Sepehr Azari

Examiner (ID: 9745, Phone: (571)270-7903 , Office: P/2699 )

Most Active Art Unit
2621
Art Unit(s)
2699, 2691, 2621
Total Applications
620
Issued Applications
452
Pending Applications
49
Abandoned Applications
133

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15472953 [patent_doc_number] => 10552354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Managing starvation in a distributed arbitration scheme [patent_app_type] => utility [patent_app_number] => 16/360412 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360412
Managing starvation in a distributed arbitration scheme Mar 20, 2019 Issued
Array ( [id] => 17401594 [patent_doc_number] => 20220043684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MEMORIES COMPRISING PROCESSOR PROFILES [patent_app_type] => utility [patent_app_number] => 17/415879 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17415879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/415879
MEMORIES COMPRISING PROCESSOR PROFILES Mar 6, 2019 Abandoned
Array ( [id] => 15773065 [patent_doc_number] => 20200117550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR BACKING UP DATA [patent_app_type] => utility [patent_app_number] => 16/288102 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288102
Dynamic block chain system using metadata for backing up data based on digest rules Feb 27, 2019 Issued
Array ( [id] => 15412271 [patent_doc_number] => 20200026458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => SYSTEMS AND METHODS AND SYSTEMS FOR READING DATA SEQUENTIALLY ON A MEDIA [patent_app_type] => utility [patent_app_number] => 16/288344 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288344 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288344
Systems and methods and systems for reading data sequentially on a media Feb 27, 2019 Issued
Array ( [id] => 15578363 [patent_doc_number] => 10579564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => System on chip (SoC), mobile electronic device including the same, and method of operating the SoC [patent_app_type] => utility [patent_app_number] => 16/273621 [patent_app_country] => US [patent_app_date] => 2019-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10202 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/273621
System on chip (SoC), mobile electronic device including the same, and method of operating the SoC Feb 11, 2019 Issued
Array ( [id] => 16957714 [patent_doc_number] => 11061574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Accelerated data processing in SSDs comprises SPAs an APM and host processor whereby the SPAs has multiple of SPEs [patent_app_type] => utility [patent_app_number] => 16/270434 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270434
Accelerated data processing in SSDs comprises SPAs an APM and host processor whereby the SPAs has multiple of SPEs Feb 6, 2019 Issued
Array ( [id] => 16224750 [patent_doc_number] => 20200249867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => Sharing Processor Cores in a Data Storage System [patent_app_type] => utility [patent_app_number] => 16/263263 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263263
Sharing processor cores in a multi-threading block i/o request processing data storage system Jan 30, 2019 Issued
Array ( [id] => 16292169 [patent_doc_number] => 10769020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Sharing private space among data storage system data rebuild and data deduplication components to minimize private space overhead [patent_app_type] => utility [patent_app_number] => 16/263347 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6558 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263347
Sharing private space among data storage system data rebuild and data deduplication components to minimize private space overhead Jan 30, 2019 Issued
Array ( [id] => 16032123 [patent_doc_number] => 10678480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-09 [patent_title] => Dynamic adjustment of a process scheduler in a data storage system based on loading of the data storage system during a preceding sampling time period [patent_app_type] => utility [patent_app_number] => 16/263301 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9962 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263301 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263301
Dynamic adjustment of a process scheduler in a data storage system based on loading of the data storage system during a preceding sampling time period Jan 30, 2019 Issued
Array ( [id] => 15919207 [patent_doc_number] => 10656841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-19 [patent_title] => Reducing per-I/O CPU overhead by queueing and batching read requests and read completion notifications [patent_app_type] => utility [patent_app_number] => 16/251024 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6987 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251024
Reducing per-I/O CPU overhead by queueing and batching read requests and read completion notifications Jan 16, 2019 Issued
Array ( [id] => 17364917 [patent_doc_number] => 11231938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Parameter configuration method for a display device having a plurality of drivers for each connected component [patent_app_type] => utility [patent_app_number] => 16/768130 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 14833 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16768130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/768130
Parameter configuration method for a display device having a plurality of drivers for each connected component Jan 15, 2019 Issued
Array ( [id] => 16179109 [patent_doc_number] => 20200226077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => NETWORK INTERFACE DEVICE WITH NON-VOLATILE MEMOERY EXPREESS OVER FABRICS (NVME-OF) SUPPORT OVER WIDE-AREA NETWORKS [patent_app_type] => utility [patent_app_number] => 16/248666 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248666
NETWORK INTERFACE DEVICE WITH NON-VOLATILE MEMOERY EXPREESS OVER FABRICS (NVME-OF) SUPPORT OVER WIDE-AREA NETWORKS Jan 14, 2019 Abandoned
Array ( [id] => 16371233 [patent_doc_number] => 10802994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Caliberating a plurality of conductances of columns in memristor crossbar based computing [patent_app_type] => utility [patent_app_number] => 16/242660 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4689 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242660
Caliberating a plurality of conductances of columns in memristor crossbar based computing Jan 7, 2019 Issued
Array ( [id] => 16651854 [patent_doc_number] => 10929029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Memory controller and method for accessing memory modules and processing sub-modules [patent_app_type] => utility [patent_app_number] => 16/239542 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6745 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239542
Memory controller and method for accessing memory modules and processing sub-modules Jan 3, 2019 Issued
Array ( [id] => 16385283 [patent_doc_number] => 10810121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Data merge method for rewritable non-volatile memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 16/239535 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10088 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239535
Data merge method for rewritable non-volatile memory storage device and memory control circuit unit Jan 3, 2019 Issued
Array ( [id] => 16017915 [patent_doc_number] => 20200183801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => TRANSFERRING A WRITABLE DATA SET TO A CLOUD SERVICE [patent_app_type] => utility [patent_app_number] => 16/215971 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215971
Transferring a writable data set to a cloud service that is separate from the writable data set and terminate a snapshot after transfer Dec 10, 2018 Issued
Array ( [id] => 14472563 [patent_doc_number] => 20190187925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => STORAGE SYSTEM, CONTROL DEVICE, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/216244 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216244
Deduplication storage system having garbage collection control method Dec 10, 2018 Issued
Array ( [id] => 16408860 [patent_doc_number] => 10817413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data [patent_app_type] => utility [patent_app_number] => 16/216160 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216160
Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data Dec 10, 2018 Issued
Array ( [id] => 15757987 [patent_doc_number] => 10621107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Translation lookaside buffer (TLB) clustering system for checking multiple memory address translation entries each mapping a viritual address offset [patent_app_type] => utility [patent_app_number] => 16/215840 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215840
Translation lookaside buffer (TLB) clustering system for checking multiple memory address translation entries each mapping a viritual address offset Dec 10, 2018 Issued
Array ( [id] => 14189147 [patent_doc_number] => 20190114279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => SCALABLE STORAGE BOX [patent_app_type] => utility [patent_app_number] => 16/214668 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214668
Scalable pooled NVMe storage box that comprises a PCIe switch further connected to one or more switches and switch ports Dec 9, 2018 Issued
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