Search

Sepehr Azari

Examiner (ID: 9745, Phone: (571)270-7903 , Office: P/2699 )

Most Active Art Unit
2621
Art Unit(s)
2699, 2691, 2621
Total Applications
620
Issued Applications
452
Pending Applications
49
Abandoned Applications
133

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14983019 [patent_doc_number] => 10445427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Semantic parsing with knowledge-based editor for execution of operations [patent_app_type] => utility [patent_app_number] => 15/730001 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11291 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730001
Semantic parsing with knowledge-based editor for execution of operations Oct 10, 2017 Issued
Array ( [id] => 16972427 [patent_doc_number] => 11068399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Technologies for enforcing coherence ordering in consumer polling interactions by receiving snoop request by controller and update value of cache line [patent_app_type] => utility [patent_app_number] => 15/720379 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10317 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720379 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720379
Technologies for enforcing coherence ordering in consumer polling interactions by receiving snoop request by controller and update value of cache line Sep 28, 2017 Issued
Array ( [id] => 12153695 [patent_doc_number] => 20180024959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'MOBILE COMPUTING DEVICE RECONFIGURATION IS RESPONSE TO ENVIRONMENTAL FACTORS INCLUDING DOWNLOADING HARDWARE AND SOFTWARE ASSOCIATED WITH MULTIPLE USERS OF THE MOBILE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/712169 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8717 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712169
Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module Sep 21, 2017 Issued
Array ( [id] => 15182477 [patent_doc_number] => 20190361830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => ELECTRONIC DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/477718 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/477718
Electronic apparatus device and control method including a host communicating with a plurality of connectors in a lump through a bus line Sep 17, 2017 Issued
Array ( [id] => 12121908 [patent_doc_number] => 20180005494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Configuring Point-of-Sale (POS) Applications to Communicate with Peripheral Devices in a POS System' [patent_app_type] => utility [patent_app_number] => 15/703315 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703315
Configuring point-of-sale (POS) applications based on a priority level in order to communicate with peripheral devices in a POS system Sep 12, 2017 Issued
Array ( [id] => 12123066 [patent_doc_number] => 20180006652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'APPARATUS FOR PROVIDING A SHARED REFERENCE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/702620 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702620
Apparatus for providing shared reference device wherein an internal device is calibrated using reference device via calibrated circuit Sep 11, 2017 Issued
Array ( [id] => 12756310 [patent_doc_number] => 20180143937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => MULTISLOT LINK LAYER FLIT WHEREIN FLIT INCLUDES THREE OR MORE SLOTS WHEREBY EACH SLOT COMPRISES RESPECTIVE CONTROL FIELD AND RESPECTIVE PAYLOAD FIELD [patent_app_type] => utility [patent_app_number] => 15/692613 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692613
Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field Aug 30, 2017 Issued
Array ( [id] => 11996076 [patent_doc_number] => 20170300231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'STORAGE SYSTEM, METHOD, AND APPARATUS FOR PROCESSING OPERATION REQUEST' [patent_app_type] => utility [patent_app_number] => 15/641583 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14986 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641583
Storage system, method, and apparatus for processing multi-layer protocol encapsulation or decapsulation operation requests Jul 4, 2017 Issued
Array ( [id] => 12374115 [patent_doc_number] => 09959593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Memory controller having plurality of channels that provides simultaneous access to data when accessing unified graphics memory [patent_app_type] => utility [patent_app_number] => 15/638868 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5828 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638868 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638868
Memory controller having plurality of channels that provides simultaneous access to data when accessing unified graphics memory Jun 29, 2017 Issued
Array ( [id] => 13240995 [patent_doc_number] => 10133696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Bridge, an asynchronous channel based bus, and a message broker to provide asynchronous communication [patent_app_type] => utility [patent_app_number] => 15/635053 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635053 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635053
Bridge, an asynchronous channel based bus, and a message broker to provide asynchronous communication Jun 26, 2017 Issued
Array ( [id] => 11989343 [patent_doc_number] => 20170293498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'DYNAMICALLY MANAGING A SERIAL PORT INTERFACE OF VIRTUALIZATION SOFTWARE' [patent_app_type] => utility [patent_app_number] => 15/633536 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633536
Dynamically managing a serial port interface connected to a direct console user interface (DCUI) of virtualization software using headless flags Jun 25, 2017 Issued
Array ( [id] => 12053383 [patent_doc_number] => 20170329727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTAIN PROGRAMMABLE TARGET RATIO OF ONES AND ZEROS IN SIGNAL LINES' [patent_app_type] => utility [patent_app_number] => 15/608846 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12881 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608846
Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines May 29, 2017 Issued
Array ( [id] => 13041327 [patent_doc_number] => 10042799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-07 [patent_title] => Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system [patent_app_type] => utility [patent_app_number] => 15/603434 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603434 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603434
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system May 22, 2017 Issued
Array ( [id] => 17938225 [patent_doc_number] => 11472665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Elevator car position detection sensor that determines a phase of an alternating-current voltage corresponding to a frequency of an excitation magnetic field [patent_app_type] => utility [patent_app_number] => 16/483043 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3344 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/483043
Elevator car position detection sensor that determines a phase of an alternating-current voltage corresponding to a frequency of an excitation magnetic field May 9, 2017 Issued
Array ( [id] => 11868131 [patent_doc_number] => 20170235416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'PEN/TOUCH TABLET COMPUTER HAVING MULTIPLE OPERATION MODES AND METHOD FOR SWITCHING OPERATION MODES' [patent_app_type] => utility [patent_app_number] => 15/583522 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11114 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583522 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583522
Pen/touch tablet computer having multiple operation modes and method for switching operation modes Apr 30, 2017 Issued
Array ( [id] => 15198133 [patent_doc_number] => 10496561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies [patent_app_type] => utility [patent_app_number] => 15/490036 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490036 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490036
Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies Apr 17, 2017 Issued
Array ( [id] => 13497481 [patent_doc_number] => 20180300283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => MULTI-HOST PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SWITCHING [patent_app_type] => utility [patent_app_number] => 15/490490 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490490
Multi-host peripheral component interconnect express (PCIe) switching based on interrupt vector from PCIe device Apr 17, 2017 Issued
Array ( [id] => 11838776 [patent_doc_number] => 20170220496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD AND APPARATUS FOR DECREASING PRESENTATION LATENCY' [patent_app_type] => utility [patent_app_number] => 15/490745 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7975 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490745 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490745
Method and apparatus for improving decreasing presentation latency in response to receipt of latency reduction mode signal Apr 17, 2017 Issued
Array ( [id] => 12025857 [patent_doc_number] => 20170315956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'PCIe DEVICE FOR SUPPORTING SRIS' [patent_app_type] => utility [patent_app_number] => 15/489125 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489125
PCIe device for supporting with a separate reference clock with independent spread spectrum clocking (SSC)(SRIS) Apr 16, 2017 Issued
Array ( [id] => 15075359 [patent_doc_number] => 10467170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Storage array including a bridge module interconnect to provide bridge connections to different protocol bridge protocol modules [patent_app_type] => utility [patent_app_number] => 15/489698 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489698
Storage array including a bridge module interconnect to provide bridge connections to different protocol bridge protocol modules Apr 16, 2017 Issued
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