Search

Sergio Jose Curbelo Iii

Examiner (ID: 16302, Phone: (571)270-7172 , Office: P/2193 )

Most Active Art Unit
2193
Art Unit(s)
2166, 2193
Total Applications
91
Issued Applications
50
Pending Applications
0
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16528821 [patent_doc_number] => 20200402902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => CONNECTION OF SEVERAL CIRCUITS OF AN ELECTRONIC CHIP [patent_app_type] => utility [patent_app_number] => 16/901449 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901449
Connection of several circuits of an electronic chip Jun 14, 2020 Issued
Array ( [id] => 17652954 [patent_doc_number] => 11355696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Magnetic tunnel junction structures and related methods [patent_app_type] => utility [patent_app_number] => 16/900550 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6306 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900550 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900550
Magnetic tunnel junction structures and related methods Jun 11, 2020 Issued
Array ( [id] => 18372000 [patent_doc_number] => 11652183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Infrared photodetectors [patent_app_type] => utility [patent_app_number] => 16/899759 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4577 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899759
Infrared photodetectors Jun 11, 2020 Issued
Array ( [id] => 17295411 [patent_doc_number] => 20210391250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => VIA STRUCTURES FOR USE IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/899543 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899543
Via structures for use in semiconductor devices Jun 10, 2020 Issued
Array ( [id] => 16545175 [patent_doc_number] => 20200411590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MRAM MEMORY CELL LAYOUT FOR MINIMIZING BITCELL AREA [patent_app_type] => utility [patent_app_number] => 16/893010 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893010
MRAM memory cell layout for minimizing bitcell area Jun 3, 2020 Issued
Array ( [id] => 17277925 [patent_doc_number] => 20210384123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => WELL-CONTROLLED EDGE-TO-EDGE SPACING BETWEEN ADJACENT INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/891143 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891143 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891143
Well-controlled edge-to-edge spacing between adjacent interconnects Jun 2, 2020 Issued
Array ( [id] => 16316241 [patent_doc_number] => 20200294979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/891139 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891139
Package-on-package (PoP) semiconductor package and electronic system including the same Jun 2, 2020 Issued
Array ( [id] => 16858527 [patent_doc_number] => 20210159272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/887541 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887541
Magnetic memory devices May 28, 2020 Issued
Array ( [id] => 17263000 [patent_doc_number] => 20210375985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/886648 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886648
Semiconductor structure and method of forming the same May 27, 2020 Issued
Array ( [id] => 16731381 [patent_doc_number] => 20210098529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY DEVICE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/886480 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886480 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886480
Magnetic random access memory device and formation method thereof May 27, 2020 Issued
Array ( [id] => 17263002 [patent_doc_number] => 20210375987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD FOR MRAM TOP ELECTRODE CONNECTION [patent_app_type] => utility [patent_app_number] => 16/884353 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884353
Method for MRAM top electrode connection May 26, 2020 Issued
Array ( [id] => 16973680 [patent_doc_number] => 11069662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/882517 [patent_app_country] => US [patent_app_date] => 2020-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882517
Semiconductor package and manufacturing method thereof May 23, 2020 Issued
Array ( [id] => 16301175 [patent_doc_number] => 20200286898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => Integrated Assemblies Having Dielectric Regions Along Conductive Structures, and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 16/880900 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880900
Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies May 20, 2020 Issued
Array ( [id] => 17438981 [patent_doc_number] => 11264322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/877502 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4946 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877502 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877502
Semiconductor structure and manufacturing method thereof May 18, 2020 Issued
Array ( [id] => 17439047 [patent_doc_number] => 11264388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Microelectronic devices including decoupling capacitors, and related apparatuses, electronic systems, and methods [patent_app_type] => utility [patent_app_number] => 16/876362 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11059 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876362
Microelectronic devices including decoupling capacitors, and related apparatuses, electronic systems, and methods May 17, 2020 Issued
Array ( [id] => 17758127 [patent_doc_number] => 11398426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Integrated-circuit devices and circuitry comprising the same [patent_app_type] => utility [patent_app_number] => 16/876591 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8021 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876591
Integrated-circuit devices and circuitry comprising the same May 17, 2020 Issued
Array ( [id] => 16973627 [patent_doc_number] => 11069607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Metal option structure of semiconductor device [patent_app_type] => utility [patent_app_number] => 16/876012 [patent_app_country] => US [patent_app_date] => 2020-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6007 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876012
Metal option structure of semiconductor device May 15, 2020 Issued
Array ( [id] => 19110263 [patent_doc_number] => 11963397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Display panel, method for manufacturing the same and display device [patent_app_type] => utility [patent_app_number] => 17/280725 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 15392 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17280725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/280725
Display panel, method for manufacturing the same and display device May 14, 2020 Issued
Array ( [id] => 16545038 [patent_doc_number] => 20200411453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => Integrated Circuit Layout, Integrated Circuit, and Method for Fabricating the Same [patent_app_type] => utility [patent_app_number] => 16/869916 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869916
Integrated circuit layout, integrated circuit, and method for fabricating the same May 7, 2020 Issued
Array ( [id] => 16738924 [patent_doc_number] => 10964588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Selective ILD deposition for fully aligned via with airgap [patent_app_type] => utility [patent_app_number] => 16/868475 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 8412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868475
Selective ILD deposition for fully aligned via with airgap May 5, 2020 Issued
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