Sergio Jose Curbelo Iii
Examiner (ID: 16302, Phone: (571)270-7172 , Office: P/2193 )
Most Active Art Unit | 2193 |
Art Unit(s) | 2166, 2193 |
Total Applications | 91 |
Issued Applications | 50 |
Pending Applications | 0 |
Abandoned Applications | 41 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16081201
[patent_doc_number] => 20200194587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => UNIFORM BOTTOM SPACER FOR VFET DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/797208
[patent_app_country] => US
[patent_app_date] => 2020-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6436
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797208
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/797208 | Uniform bottom spacer for VFET devices | Feb 20, 2020 | Issued |
Array
(
[id] => 16560402
[patent_doc_number] => 20210005551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/793366
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5658
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793366
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793366 | Semiconductor device | Feb 17, 2020 | Issued |
Array
(
[id] => 15969827
[patent_doc_number] => 20200168665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => IMAGING DEVICE, MANUFACTURING DEVICE, AND MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/778053
[patent_app_country] => US
[patent_app_date] => 2020-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11131
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778053
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/778053 | Imaging device, manufacturing device, and manufacturing method | Jan 30, 2020 | Issued |
Array
(
[id] => 16996096
[patent_doc_number] => 20210234516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-29
[patent_title] => INTEGRATED CIRCUITS CONTAINING VERTICALLY-INTEGRATED CAPACITOR-AVALANCHE DIODE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/775573
[patent_app_country] => US
[patent_app_date] => 2020-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8447
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16775573
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/775573 | Integrated circuits containing vertically-integrated capacitor-avalanche diode structures | Jan 28, 2020 | Issued |
Array
(
[id] => 17048023
[patent_doc_number] => 11101213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => EFuse structure with multiple links
[patent_app_type] => utility
[patent_app_number] => 16/774893
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5112
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774893
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774893 | EFuse structure with multiple links | Jan 27, 2020 | Issued |
Array
(
[id] => 16521556
[patent_doc_number] => 10872781
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-22
[patent_title] => Semiconductor device and a method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/774823
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 5545
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774823
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774823 | Semiconductor device and a method for fabricating the same | Jan 27, 2020 | Issued |
Array
(
[id] => 17166313
[patent_doc_number] => 11152426
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Memory device using an etch stop dielectric layer and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 16/743267
[patent_app_country] => US
[patent_app_date] => 2020-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 13062
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743267
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/743267 | Memory device using an etch stop dielectric layer and methods for forming the same | Jan 14, 2020 | Issued |
Array
(
[id] => 16645670
[patent_doc_number] => 10923538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 16/741599
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 19080
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/741599 | Display device | Jan 12, 2020 | Issued |
Array
(
[id] => 17977680
[patent_doc_number] => 11494542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-08
[patent_title] => Semiconductor device, method of generating layout diagram and system for same
[patent_app_type] => utility
[patent_app_number] => 16/741440
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 10913
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741440
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/741440 | Semiconductor device, method of generating layout diagram and system for same | Jan 12, 2020 | Issued |
Array
(
[id] => 16911522
[patent_doc_number] => 11043572
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-22
[patent_title] => Metal gate structure and methods thereof
[patent_app_type] => utility
[patent_app_number] => 16/741381
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 6158
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741381
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/741381 | Metal gate structure and methods thereof | Jan 12, 2020 | Issued |
Array
(
[id] => 15906311
[patent_doc_number] => 20200152676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => METHOD OF MAKING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/738887
[patent_app_country] => US
[patent_app_date] => 2020-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8230
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738887
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/738887 | Method of making a semiconductor device | Jan 8, 2020 | Issued |
Array
(
[id] => 17032905
[patent_doc_number] => 11094723
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-17
[patent_title] => Semiconductor device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/738943
[patent_app_country] => US
[patent_app_date] => 2020-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 8122
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738943
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/738943 | Semiconductor device and method of forming the same | Jan 8, 2020 | Issued |
Array
(
[id] => 16617402
[patent_doc_number] => 20210036055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => MEMORY DEVICE AND SEMICONDUCTOR DIE, AND METHOD OF FABRICATING MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/739016
[patent_app_country] => US
[patent_app_date] => 2020-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8529
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739016
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/739016 | Memory device and semiconductor die, and method of fabricating memory device | Jan 8, 2020 | Issued |
Array
(
[id] => 16951692
[patent_doc_number] => 20210210384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => SELF-ALIGNED GATE CONTACT COMPATIBLE CROSS COUPLE CONTACT FORMATION
[patent_app_type] => utility
[patent_app_number] => 16/735861
[patent_app_country] => US
[patent_app_date] => 2020-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4203
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735861
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/735861 | Self-aligned gate contact compatible cross couple contact formation | Jan 6, 2020 | Issued |
Array
(
[id] => 16707793
[patent_doc_number] => 10957737
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Symmetrical qubits with reduced far-field radiation
[patent_app_type] => utility
[patent_app_number] => 16/735851
[patent_app_country] => US
[patent_app_date] => 2020-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8013
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735851
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/735851 | Symmetrical qubits with reduced far-field radiation | Jan 6, 2020 | Issued |
Array
(
[id] => 17652958
[patent_doc_number] => 11355700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-07
[patent_title] => Semiconductor device and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/732359
[patent_app_country] => US
[patent_app_date] => 2020-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 4062
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732359
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/732359 | Semiconductor device and method for fabricating the same | Jan 1, 2020 | Issued |
Array
(
[id] => 17224700
[patent_doc_number] => 11177210
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-16
[patent_title] => Integrated circuit with non-functional structures
[patent_app_type] => utility
[patent_app_number] => 16/731522
[patent_app_country] => US
[patent_app_date] => 2019-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2916
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731522
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/731522 | Integrated circuit with non-functional structures | Dec 30, 2019 | Issued |
Array
(
[id] => 16502703
[patent_doc_number] => 10868102
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-15
[patent_title] => Organic light emitting display panel and display device
[patent_app_type] => utility
[patent_app_number] => 16/732082
[patent_app_country] => US
[patent_app_date] => 2019-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 6239
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732082
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/732082 | Organic light emitting display panel and display device | Dec 30, 2019 | Issued |
Array
(
[id] => 16866042
[patent_doc_number] => 11024797
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Under-cut via electrode for sub 60 nm etchless MRAM devices by decoupling the via etch process
[patent_app_type] => utility
[patent_app_number] => 16/728043
[patent_app_country] => US
[patent_app_date] => 2019-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 2076
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728043
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/728043 | Under-cut via electrode for sub 60 nm etchless MRAM devices by decoupling the via etch process | Dec 26, 2019 | Issued |
Array
(
[id] => 16920481
[patent_doc_number] => 20210193573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => METHODS OF FORMING A CONDUCTIVE CONTACT STRUCTURE TO AN EMBEDDED MEMORY DEVICE ON AN IC PRODUCT AND A CORRESPONDING IC PRODUCT
[patent_app_type] => utility
[patent_app_number] => 16/726497
[patent_app_country] => US
[patent_app_date] => 2019-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6752
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726497
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/726497 | Methods of forming a conductive contact structure to an embedded memory device on an IC product and a corresponding IC product | Dec 23, 2019 | Issued |