![](/images/general/no_picture/200_user.png)
Sergio Jose Curbelo Iii
Examiner (ID: 16302, Phone: (571)270-7172 , Office: P/2193 )
Most Active Art Unit | 2193 |
Art Unit(s) | 2166, 2193 |
Total Applications | 91 |
Issued Applications | 50 |
Pending Applications | 0 |
Abandoned Applications | 41 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16410112
[patent_doc_number] => 10818677
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-27
[patent_title] => Layout of static random access memory periphery circuit
[patent_app_type] => utility
[patent_app_number] => 16/502790
[patent_app_country] => US
[patent_app_date] => 2019-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 11452
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502790
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/502790 | Layout of static random access memory periphery circuit | Jul 2, 2019 | Issued |
Array
(
[id] => 15274735
[patent_doc_number] => 20190386102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE
[patent_app_type] => utility
[patent_app_number] => 16/455096
[patent_app_country] => US
[patent_app_date] => 2019-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455096
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/455096 | Vertical field effect transistor with reduced gate to source/drain capacitance | Jun 26, 2019 | Issued |
Array
(
[id] => 15274733
[patent_doc_number] => 20190386101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE
[patent_app_type] => utility
[patent_app_number] => 16/455045
[patent_app_country] => US
[patent_app_date] => 2019-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6340
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455045
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/455045 | Vertical field effect transistor with reduced gate to source/drain capacitance | Jun 26, 2019 | Issued |
Array
(
[id] => 15274953
[patent_doc_number] => 20190386211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => Sub 60nm Etchless MRAM Devices by Ion Beam Etching Fabricated T-Shaped Bottom Electrode
[patent_app_type] => utility
[patent_app_number] => 16/452909
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452909
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/452909 | Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode | Jun 25, 2019 | Issued |
Array
(
[id] => 16372597
[patent_doc_number] => 10804363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-13
[patent_title] => Three-dimensional semiconductor memory device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/445815
[patent_app_country] => US
[patent_app_date] => 2019-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 63
[patent_figures_cnt] => 66
[patent_no_of_words] => 12104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445815
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445815 | Three-dimensional semiconductor memory device and method of fabricating the same | Jun 18, 2019 | Issued |
Array
(
[id] => 17310331
[patent_doc_number] => 11211458
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-28
[patent_title] => Photocatalytic device based on rare-earth elements: methods of manufacture and use
[patent_app_type] => utility
[patent_app_number] => 16/445789
[patent_app_country] => US
[patent_app_date] => 2019-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4429
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445789
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445789 | Photocatalytic device based on rare-earth elements: methods of manufacture and use | Jun 18, 2019 | Issued |
Array
(
[id] => 15300133
[patent_doc_number] => 20190393202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-26
[patent_title] => DISPLAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/445777
[patent_app_country] => US
[patent_app_date] => 2019-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7236
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445777
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445777 | Display substrate and fabrication method thereof, display panel and display device | Jun 18, 2019 | Issued |
Array
(
[id] => 16594088
[patent_doc_number] => 10903365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-26
[patent_title] => Transistors with uniform source/drain epitaxy
[patent_app_type] => utility
[patent_app_number] => 16/445823
[patent_app_country] => US
[patent_app_date] => 2019-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6456
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445823
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445823 | Transistors with uniform source/drain epitaxy | Jun 18, 2019 | Issued |
Array
(
[id] => 16280366
[patent_doc_number] => 10763408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Backlight including light emitting module and light reflective members
[patent_app_type] => utility
[patent_app_number] => 16/442412
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 8986
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442412
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/442412 | Backlight including light emitting module and light reflective members | Jun 13, 2019 | Issued |
Array
(
[id] => 17130760
[patent_doc_number] => 20210305529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => LIGHT EMITTING DEVICE COMPRISING PEROVSKITE CHARGE TRANSPORT LAYER AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/252268
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10946
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17252268
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/252268 | LIGHT EMITTING DEVICE COMPRISING PEROVSKITE CHARGE TRANSPORT LAYER AND MANUFACTURING METHOD THEREOF | Jun 13, 2019 | Pending |
Array
(
[id] => 16234076
[patent_doc_number] => 10741640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => Dielectric and isolation lower Fin material for Fin-based electronics
[patent_app_type] => utility
[patent_app_number] => 16/435250
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 56
[patent_no_of_words] => 7410
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435250
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435250 | Dielectric and isolation lower Fin material for Fin-based electronics | Jun 6, 2019 | Issued |
Array
(
[id] => 14843363
[patent_doc_number] => 20190280082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => Methods Of Forming An Array Of Capacitors, Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor, Arrays Of Capacitors, And Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor
[patent_app_type] => utility
[patent_app_number] => 16/426419
[patent_app_country] => US
[patent_app_date] => 2019-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11882
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426419
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/426419 | Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor | May 29, 2019 | Issued |
Array
(
[id] => 14904683
[patent_doc_number] => 20190296107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/423641
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11973
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423641
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/423641 | Semiconductor device and method for fabricating the same | May 27, 2019 | Issued |
Array
(
[id] => 15504111
[patent_doc_number] => 20200052244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => DISPLAY AREA DRILLING AND PACKAGING STRUCTURE AND METHOD, DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/422496
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422496
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/422496 | Display area drilling and packaging structure and method, display device | May 23, 2019 | Issued |
Array
(
[id] => 15260219
[patent_doc_number] => 20190378843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => Integrated Assemblies Having Dielectric Regions Along Conductive Structures, and Methods of Forming Integrated Assemblies
[patent_app_type] => utility
[patent_app_number] => 16/419978
[patent_app_country] => US
[patent_app_date] => 2019-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4381
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419978
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/419978 | Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies | May 21, 2019 | Issued |
Array
(
[id] => 15889451
[patent_doc_number] => 10651078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Selective ILD deposition for fully aligned via with airgap
[patent_app_type] => utility
[patent_app_number] => 16/406115
[patent_app_country] => US
[patent_app_date] => 2019-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 35
[patent_no_of_words] => 8355
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406115
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/406115 | Selective ILD deposition for fully aligned via with airgap | May 7, 2019 | Issued |
Array
(
[id] => 14753355
[patent_doc_number] => 20190259851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY
[patent_app_type] => utility
[patent_app_number] => 16/401335
[patent_app_country] => US
[patent_app_date] => 2019-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10461
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401335
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/401335 | Circuits using gate-all-around technology | May 1, 2019 | Issued |
Array
(
[id] => 15147395
[patent_doc_number] => 20190352175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => MEMS SENSOR, MEMS SENSOR SYSTEM AND METHOD FOR PRODUCING A MEMS SENSOR SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/400365
[patent_app_country] => US
[patent_app_date] => 2019-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6718
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400365
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/400365 | MEMS sensor, MEMS sensor system and method for producing a MEMS sensor system | Apr 30, 2019 | Issued |
Array
(
[id] => 15274531
[patent_doc_number] => 20190386000
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => Integrated Standard Cell Structure
[patent_app_type] => utility
[patent_app_number] => 16/397021
[patent_app_country] => US
[patent_app_date] => 2019-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8479
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397021
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/397021 | Integrated standard cell structure | Apr 28, 2019 | Issued |
Array
(
[id] => 16948335
[patent_doc_number] => 20210207026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => RED PHOSPHOR AND LIGHT EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/056631
[patent_app_country] => US
[patent_app_date] => 2019-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4282
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17056631
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/056631 | Red phosphor and light emitting device | Apr 7, 2019 | Issued |