Search

Seungsook Ham

Supervisory Patent Examiner (ID: 8740, Phone: (571)272-2405 , Office: P/2800 )

Most Active Art Unit
2817
Art Unit(s)
2878, 4154, 2800, 2817
Total Applications
630
Issued Applications
510
Pending Applications
27
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19848821 [patent_doc_number] => 20250094172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Processor Supporting Position-Independent Addressing [patent_app_type] => utility [patent_app_number] => 18/969134 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18969134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/969134
Processor Supporting Position-Independent Addressing Dec 3, 2024 Pending
Array ( [id] => 20000606 [patent_doc_number] => 20250138828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => PIPELINE OPTIMIZATION WITH VARIABLE LATENCY EXECUTION [patent_app_type] => utility [patent_app_number] => 18/932738 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932738
PIPELINE OPTIMIZATION WITH VARIABLE LATENCY EXECUTION Oct 30, 2024 Pending
Array ( [id] => 20000605 [patent_doc_number] => 20250138827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => METHODS AND APPARATUS FOR PROCESSING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/927890 [patent_app_country] => US [patent_app_date] => 2024-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/927890
METHODS AND APPARATUS FOR PROCESSING INSTRUCTIONS Oct 25, 2024 Pending
Array ( [id] => 20494261 [patent_doc_number] => 12536131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Vector computational unit [patent_app_type] => utility [patent_app_number] => 18/830458 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830458
Vector computational unit Sep 9, 2024 Issued
Array ( [id] => 19603184 [patent_doc_number] => 20240394064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Apparatus and Method for Implementing a Loop Prediction of Multiple Basic Blocks [patent_app_type] => utility [patent_app_number] => 18/796021 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18796021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/796021
Apparatus and Method for Implementing a Loop Prediction of Multiple Basic Blocks Aug 5, 2024 Pending
Array ( [id] => 19711194 [patent_doc_number] => 20250021336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => POLARITY-BASED DATA PREFETCHER WITH UNDERLYING STRIDE DETECTION [patent_app_type] => utility [patent_app_number] => 18/768088 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768088
POLARITY-BASED DATA PREFETCHER WITH UNDERLYING STRIDE DETECTION Jul 9, 2024 Pending
Array ( [id] => 19747844 [patent_doc_number] => 20250036409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/756084 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756084 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756084
PROCESSOR Jun 26, 2024 Pending
Array ( [id] => 20166623 [patent_doc_number] => 20250258670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => RESERVATION STATION WITH MULTIPLE ENTRY TYPES [patent_app_type] => utility [patent_app_number] => 18/742976 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742976
RESERVATION STATION WITH MULTIPLE ENTRY TYPES Jun 12, 2024 Pending
Array ( [id] => 19451020 [patent_doc_number] => 20240311150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => METHOD FOR SECURE, SIMPLE, AND FAST SPECULATIVE EXECUTION [patent_app_type] => utility [patent_app_number] => 18/674820 [patent_app_country] => US [patent_app_date] => 2024-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674820 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674820
METHOD FOR SECURE, SIMPLE, AND FAST SPECULATIVE EXECUTION May 24, 2024 Pending
Array ( [id] => 20380422 [patent_doc_number] => 20250362915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PREFETCH REQUEST GENERATION [patent_app_type] => utility [patent_app_number] => 18/670039 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670039 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670039
PREFETCH REQUEST GENERATION May 20, 2024 Pending
Array ( [id] => 19303251 [patent_doc_number] => 20240231831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => VECTOR INDEX REGISTERS [patent_app_type] => utility [patent_app_number] => 18/612143 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612143
VECTOR INDEX REGISTERS Mar 20, 2024 Pending
Array ( [id] => 20195393 [patent_doc_number] => 20250272103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SPECULATION THROTTLING [patent_app_type] => utility [patent_app_number] => 18/589892 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589892 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589892
SPECULATION THROTTLING Feb 27, 2024 Pending
Array ( [id] => 19219882 [patent_doc_number] => 20240184586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => MECHANISM TO QUEUE MULTIPLE STREAMS TO RUN ON STREAMING ENGINE [patent_app_type] => utility [patent_app_number] => 18/438609 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438609
MECHANISM TO QUEUE MULTIPLE STREAMS TO RUN ON STREAMING ENGINE Feb 11, 2024 Pending
Array ( [id] => 19204860 [patent_doc_number] => 20240176759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MACHINE LEARNING PARALLELIZATION METHOD USING HOST CPU WITH MULTI-SOCKET STRUCTURE AND APPARATUS THEREFOR [patent_app_type] => utility [patent_app_number] => 18/521396 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521396
MACHINE LEARNING PARALLELIZATION METHOD USING HOST CPU WITH MULTI-SOCKET STRUCTURE AND APPARATUS THEREFOR Nov 27, 2023 Pending
Array ( [id] => 19765035 [patent_doc_number] => 12223326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Order-preserving method and system for multiple sets of load store queues of processor and related device [patent_app_type] => utility [patent_app_number] => 18/693524 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6799 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18693524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/693524
Order-preserving method and system for multiple sets of load store queues of processor and related device Nov 19, 2023 Issued
Array ( [id] => 19114797 [patent_doc_number] => 20240126547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => INSTRUCTION SET ARCHITECTURE FOR A VECTOR COMPUTATIONAL UNIT [patent_app_type] => utility [patent_app_number] => 18/490672 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490672
Instruction set architecture for a vector computational unit Oct 18, 2023 Issued
Array ( [id] => 18941728 [patent_doc_number] => 20240036867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => IMPLIED FENCE ON STREAM OPEN [patent_app_type] => utility [patent_app_number] => 18/378207 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378207
IMPLIED FENCE ON STREAM OPEN Oct 9, 2023 Pending
Array ( [id] => 18810726 [patent_doc_number] => 20230385062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ASSOCIATIVELY INDEXED CIRCULAR BUFFER [patent_app_type] => utility [patent_app_number] => 18/232531 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232531
Associatively indexed circular buffer Aug 9, 2023 Issued
Array ( [id] => 18741700 [patent_doc_number] => 20230350681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/344984 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344984
MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR Jun 29, 2023 Pending
Array ( [id] => 18711222 [patent_doc_number] => 20230333851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DSB Operation with Excluded Region [patent_app_type] => utility [patent_app_number] => 18/336704 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336704 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336704
DSB operation with excluded region Jun 15, 2023 Issued
Menu