
Seungsook Ham
Supervisory Patent Examiner (ID: 8740, Phone: (571)272-2405 , Office: P/2800 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2878, 4154, 2800, 2817 |
| Total Applications | 630 |
| Issued Applications | 510 |
| Pending Applications | 27 |
| Abandoned Applications | 93 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13721399
[patent_doc_number] => 20170371654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => SYSTEM AND METHOD FOR USING VIRTUAL VECTOR REGISTER FILES
[patent_app_type] => utility
[patent_app_number] => 15/191339
[patent_app_country] => US
[patent_app_date] => 2016-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6787
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191339
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/191339 | SYSTEM AND METHOD FOR USING VIRTUAL VECTOR REGISTER FILES | Jun 22, 2016 | Abandoned |
Array
(
[id] => 13706807
[patent_doc_number] => 20170364358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DEPENDENCY ACCUMULATION INSTRUCTION SEQUENCING
[patent_app_type] => utility
[patent_app_number] => 15/186744
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10395
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186744
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/186744 | Operation of a multi-slice processor implementing dependency accumulation instruction sequencing | Jun 19, 2016 | Issued |
Array
(
[id] => 12032709
[patent_doc_number] => 20170322808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'LOW-POWER PROCESSOR WITH SUPPORT FOR MULTIPLE PRECISION MODES'
[patent_app_type] => utility
[patent_app_number] => 15/147642
[patent_app_country] => US
[patent_app_date] => 2016-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6077
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147642
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/147642 | LOW-POWER PROCESSOR WITH SUPPORT FOR MULTIPLE PRECISION MODES | May 4, 2016 | Abandoned |
Array
(
[id] => 16217277
[patent_doc_number] => 10733091
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-04
[patent_title] => Read and write sets for ranges of instructions of transactions
[patent_app_type] => utility
[patent_app_number] => 15/145180
[patent_app_country] => US
[patent_app_date] => 2016-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 15582
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145180
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/145180 | Read and write sets for ranges of instructions of transactions | May 2, 2016 | Issued |
Array
(
[id] => 16185731
[patent_doc_number] => 10719056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Merging status and control data in a reservation station
[patent_app_type] => utility
[patent_app_number] => 15/144333
[patent_app_country] => US
[patent_app_date] => 2016-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5526
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15144333
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/144333 | Merging status and control data in a reservation station | May 1, 2016 | Issued |
Array
(
[id] => 12025708
[patent_doc_number] => 20170315807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-02
[patent_title] => 'HARDWARE SUPPORT FOR DYNAMIC DATA TYPES AND OPERATORS'
[patent_app_type] => utility
[patent_app_number] => 15/143753
[patent_app_country] => US
[patent_app_date] => 2016-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5771
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143753
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/143753 | HARDWARE SUPPORT FOR DYNAMIC DATA TYPES AND OPERATORS | May 1, 2016 | Abandoned |
Array
(
[id] => 11124100
[patent_doc_number] => 20160321075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'Central Processing Unit With DSP Engine And Enhanced Context Switch Capabilities'
[patent_app_type] => utility
[patent_app_number] => 15/141817
[patent_app_country] => US
[patent_app_date] => 2016-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4138
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141817
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/141817 | Central processing unit with DSP engine and enhanced context switch capabilities | Apr 27, 2016 | Issued |
Array
(
[id] => 18316718
[patent_doc_number] => 11630800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-18
[patent_title] => Programmable vision accelerator
[patent_app_type] => utility
[patent_app_number] => 15/141703
[patent_app_country] => US
[patent_app_date] => 2016-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9509
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141703
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/141703 | Programmable vision accelerator | Apr 27, 2016 | Issued |
Array
(
[id] => 16446792
[patent_doc_number] => 10838721
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-11-17
[patent_title] => Adaptive thread processing of IO requests
[patent_app_type] => utility
[patent_app_number] => 15/086647
[patent_app_country] => US
[patent_app_date] => 2016-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5107
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 399
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15086647
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/086647 | Adaptive thread processing of IO requests | Mar 30, 2016 | Issued |
Array
(
[id] => 14250113
[patent_doc_number] => 10275256
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-30
[patent_title] => Branch prediction in a computer processor
[patent_app_type] => utility
[patent_app_number] => 15/049700
[patent_app_country] => US
[patent_app_date] => 2016-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5954
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049700
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/049700 | Branch prediction in a computer processor | Feb 21, 2016 | Issued |
Array
(
[id] => 11049643
[patent_doc_number] => 20160246602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-25
[patent_title] => 'PATH SELECTION BASED ACCELERATION OF CONDITIONALS IN COARSE GRAIN RECONFIGURABLE ARRAYS (CGRAS)'
[patent_app_type] => utility
[patent_app_number] => 15/048680
[patent_app_country] => US
[patent_app_date] => 2016-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 11724
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048680
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/048680 | PATH SELECTION BASED ACCELERATION OF CONDITIONALS IN COARSE GRAIN RECONFIGURABLE ARRAYS (CGRAS) | Feb 18, 2016 | Abandoned |
Array
(
[id] => 11494355
[patent_doc_number] => 20170068539
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'HIGH PERFORMANCE ZERO BUBBLE CONDITIONAL BRANCH PREDICTION USING MICRO BRANCH TARGET BUFFER'
[patent_app_type] => utility
[patent_app_number] => 15/047617
[patent_app_country] => US
[patent_app_date] => 2016-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11157
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047617
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/047617 | High performance zero bubble conditional branch prediction using micro branch target buffer | Feb 17, 2016 | Issued |
Array
(
[id] => 11272545
[patent_doc_number] => 20160335092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'Using Very Long Instruction Word VLIW Cores In Many-Core Architectures'
[patent_app_type] => utility
[patent_app_number] => 15/046438
[patent_app_country] => US
[patent_app_date] => 2016-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7579
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046438
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/046438 | Using Very Long Instruction Word VLIW Cores In Many-Core Architectures | Feb 16, 2016 | Abandoned |
Array
(
[id] => 14489323
[patent_doc_number] => 10331449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-25
[patent_title] => Encoding instructions identifying first and second architectural register numbers
[patent_app_type] => utility
[patent_app_number] => 15/003828
[patent_app_country] => US
[patent_app_date] => 2016-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 12077
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003828
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/003828 | Encoding instructions identifying first and second architectural register numbers | Jan 21, 2016 | Issued |
Array
(
[id] => 11516246
[patent_doc_number] => 20170083320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'PREDICATED READ INSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 15/004761
[patent_app_country] => US
[patent_app_date] => 2016-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 21364
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15004761
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/004761 | PREDICATED READ INSTRUCTIONS | Jan 21, 2016 | Abandoned |
Array
(
[id] => 15058843
[patent_doc_number] => 10459725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Execution of load instructions in a processor
[patent_app_type] => utility
[patent_app_number] => 15/001628
[patent_app_country] => US
[patent_app_date] => 2016-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5595
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15001628
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/001628 | Execution of load instructions in a processor | Jan 19, 2016 | Issued |
Array
(
[id] => 11731348
[patent_doc_number] => 20170192791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'Counter to Monitor Address Conflicts'
[patent_app_type] => utility
[patent_app_number] => 14/984115
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7983
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984115
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/984115 | Counter to Monitor Address Conflicts | Dec 29, 2015 | Abandoned |
Array
(
[id] => 11731337
[patent_doc_number] => 20170192780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements'
[patent_app_type] => utility
[patent_app_number] => 14/984078
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 16123
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984078
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/984078 | Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements | Dec 29, 2015 | Abandoned |
Array
(
[id] => 11731340
[patent_doc_number] => 20170192783
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'Systems, Apparatuses, and Methods for Stride Load'
[patent_app_type] => utility
[patent_app_number] => 14/984148
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 15853
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984148
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/984148 | Systems, Apparatuses, and Methods for Stride Load | Dec 29, 2015 | Abandoned |
Array
(
[id] => 11731339
[patent_doc_number] => 20170192782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'Systems, Apparatuses, and Methods for Aggregate Gather and Stride'
[patent_app_type] => utility
[patent_app_number] => 14/984132
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 18143
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984132
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/984132 | Systems, Apparatuses, and Methods for Aggregate Gather and Stride | Dec 29, 2015 | Abandoned |