Seungsook Ham

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Array ( [id] => 18904637 [patent_doc_number] => 20240020122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => EXECUTING PHANTOM LOOPS IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 18/135481 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18719960 [patent_doc_number] => 11797304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Instruction set architecture for a vector computational unit [patent_app_type] => utility [patent_app_number] => 18/156576 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156576 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20203009 [patent_doc_number] => 12405788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Vector shuffling method, processor and electronic device [patent_app_type] => utility [patent_app_number] => 18/717956 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18717956 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 19811459 [patent_doc_number] => 12242853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-03-04 [patent_title] => Configurable vector compute engine [patent_app_type] => utility [patent_app_number] => 17/937335 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937335 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 19021943 [patent_doc_number] => 20240078114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => PROVIDING MEMORY PREFETCH INSTRUCTIONS WITH COMPLETION NOTIFICATIONS IN PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 17/939518 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939518 [rel_patent_id] =>[rel_patent_doc_number] =>)

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