Seungsook Ham

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Array ( [id] => 19558473 [patent_doc_number] => 20240370265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => BRANCH INSTRUCTION PROCESSING METHOD, SYSTEM, AND DEVICE, AND COMPUTER STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/563862 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18563862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18864178 [patent_doc_number] => 20230418614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => PROCESSOR, OPERATION METHOD, AND LOAD-STORE DEVICE FOR IMPLEMENTATION OF ACCESSING VECTOR STRIDED MEMORY [patent_app_type] => utility [patent_app_number] => 17/846030 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19459352 [patent_doc_number] => 12099845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Load reissuing using an alternate issue queue [patent_app_type] => utility [patent_app_number] => 17/807243 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5414 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18832539 [patent_doc_number] => 20230401066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => DYNAMICALLY FOLDABLE AND UNFOLDABLE INSTRUCTION FETCH PIPELINE [patent_app_type] => utility [patent_app_number] => 17/835409 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19228737 [patent_doc_number] => 12008375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Branch target buffer that stores predicted set index and predicted way number of instruction cache [patent_app_type] => utility [patent_app_number] => 17/835294 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 10686 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819512 [patent_doc_number] => 20230393852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => VECTOR COPROCESSOR WITH TIME COUNTER FOR STATICALLY DISPATCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/829909 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17809418 [patent_doc_number] => 20220261253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => VECTOR INDEX REGISTERS [patent_app_type] => utility [patent_app_number] => 17/737922 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19228732 [patent_doc_number] => 12008370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Method for preventing security attacks during speculative execution [patent_app_type] => utility [patent_app_number] => 17/737794 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7558 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18727855 [patent_doc_number] => 20230342148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MICROPROCESSOR WITH NON-CACHEABLE MEMORY LOAD PREDICTION [patent_app_type] => utility [patent_app_number] => 17/725342 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20228447 [patent_doc_number] => 12417099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Circuitry and methods for informing indirect prefetches using capabilities [patent_app_type] => utility [patent_app_number] => 17/712073 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 21708 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18677806 [patent_doc_number] => 20230315453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => FORWARD CONDITIONAL BRANCH EVENT FOR PROFILE-GUIDED-OPTIMIZATION (PGO) [patent_app_type] => utility [patent_app_number] => 17/712018 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18677821 [patent_doc_number] => 20230315468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => ENFORCING CONSISTENCY ACROSS REDUNDANT TAGGED GEOMETRIC (TAGE) BRANCH HISTORIES [patent_app_type] => utility [patent_app_number] => 17/708318 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19340723 [patent_doc_number] => 12050916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Array of pointers prefetching [patent_app_type] => utility [patent_app_number] => 17/704627 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18651545 [patent_doc_number] => 20230297381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => Load Dependent Branch Prediction [patent_app_type] => utility [patent_app_number] => 17/699855 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17690345 [patent_doc_number] => 20220197638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => GENERATING ENCRYPTED CAPABILITIES WITHIN BOUNDS [patent_app_type] => utility [patent_app_number] => 17/693748 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18007113 [patent_doc_number] => 20220365879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Throttling Schemes in Multicore Microprocessors [patent_app_type] => utility [patent_app_number] => 17/591134 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18890000 [patent_doc_number] => 11868773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Inferring future value for speculative branch resolution in a microprocessor [patent_app_type] => utility [patent_app_number] => 17/569951 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569951 [rel_patent_id] =>[rel_patent_doc_number] =>)

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