Search

Seungsook Ham

Supervisory Patent Examiner (ID: 8740, Phone: (571)272-2405 , Office: P/2800 )

Most Active Art Unit
2817
Art Unit(s)
2878, 4154, 2800, 2817
Total Applications
630
Issued Applications
510
Pending Applications
27
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17962091 [patent_doc_number] => 20220342672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => RESCHEDULING A LOAD INSTRUCTION BASED ON PAST REPLAYS [patent_app_type] => utility [patent_app_number] => 17/241726 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241726
Rescheduling a load instruction based on past replays Apr 26, 2021 Issued
Array ( [id] => 17024109 [patent_doc_number] => 20210247980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/241198 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241198
Mechanism for interrupting and resuming execution on an unprotected pipeline processor Apr 26, 2021 Issued
Array ( [id] => 16993982 [patent_doc_number] => 20210232402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => METHOD FOR VECTORIZING HEAPSORT USING HORIZONTAL AGGREGATION SIMD INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/227167 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227167
Method for vectorizing heapsort using horizontal aggregation SIMD instructions Apr 8, 2021 Issued
Array ( [id] => 16964817 [patent_doc_number] => 20210216316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => IMPLIED FENCE ON STREAM OPEN [patent_app_type] => utility [patent_app_number] => 17/216821 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216821
Implied fence on stream open Mar 29, 2021 Issued
Array ( [id] => 18966347 [patent_doc_number] => 11900117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Mechanism to queue multiple streams to run on streaming engine [patent_app_type] => utility [patent_app_number] => 17/213509 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 29761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213509
Mechanism to queue multiple streams to run on streaming engine Mar 25, 2021 Issued
Array ( [id] => 17076661 [patent_doc_number] => 11113059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Dynamic allocation of executable code for multi-architecture heterogeneous computing [patent_app_type] => utility [patent_app_number] => 17/172134 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172134
Dynamic allocation of executable code for multi-architecture heterogeneous computing Feb 9, 2021 Issued
Array ( [id] => 16950298 [patent_doc_number] => 20210208990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => APPARATUS AND METHOD FOR GENERATING PERFORMANCE MONITORING METRICS [patent_app_type] => utility [patent_app_number] => 17/125694 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125694
APPARATUS AND METHOD FOR GENERATING PERFORMANCE MONITORING METRICS Dec 16, 2020 Abandoned
Array ( [id] => 16623469 [patent_doc_number] => 20210042122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => METHOD FOR EXECUTING INSTRUCTIONS IN CPU [patent_app_type] => utility [patent_app_number] => 17/082509 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082509
Method for replenishing a thread queue with a target instruction of a jump instruction Oct 27, 2020 Issued
Array ( [id] => 18810729 [patent_doc_number] => 20230385065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor [patent_app_type] => utility [patent_app_number] => 18/031070 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/031070
Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor Oct 13, 2020 Pending
Array ( [id] => 17157826 [patent_doc_number] => 20210318877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => MICROPROCESSOR WITH INSTRUCTION FETCHING FAILURE SOLUTION [patent_app_type] => utility [patent_app_number] => 17/069191 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069191
Microprocessor with instruction fetching failure solution Oct 12, 2020 Issued
Array ( [id] => 20079812 [patent_doc_number] => 12353881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Circuitry and methods for power efficient generation of length markers for a variable length instruction set [patent_app_type] => utility [patent_app_number] => 17/033680 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 15972 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033680
Circuitry and methods for power efficient generation of length markers for a variable length instruction set Sep 25, 2020 Issued
Array ( [id] => 17484347 [patent_doc_number] => 20220091851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => System, Apparatus And Methods For Register Hardening Via A Micro-Operation [patent_app_type] => utility [patent_app_number] => 17/029335 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029335
System, Apparatus And Methods For Register Hardening Via A Micro-Operation Sep 22, 2020 Pending
Array ( [id] => 17484348 [patent_doc_number] => 20220091852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties [patent_app_type] => utility [patent_app_number] => 17/028387 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028387
Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties Sep 21, 2020 Abandoned
Array ( [id] => 16527326 [patent_doc_number] => 20200401406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => STREAMING ENGINE WITH STREAM METADATA SAVING FOR CONTEXT SWITCHING [patent_app_type] => utility [patent_app_number] => 17/011808 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011808
Streaming engine with stream metadata saving for context switching Sep 2, 2020 Issued
Array ( [id] => 16623474 [patent_doc_number] => 20210042127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Group Load Register of a Graph Streaming Processor [patent_app_type] => utility [patent_app_number] => 16/930192 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/930192
Group load register of a graph streaming processor Jul 14, 2020 Issued
Array ( [id] => 17316963 [patent_doc_number] => 20210406012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => LOADING AND STORING MATRIX DATA WITH DATATYPE CONVERSION [patent_app_type] => utility [patent_app_number] => 16/914317 [patent_app_country] => US [patent_app_date] => 2020-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914317
LOADING AND STORING MATRIX DATA WITH DATATYPE CONVERSION Jun 26, 2020 Pending
Array ( [id] => 17605873 [patent_doc_number] => 11334361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Shared pointer for local history records used by prediction circuitry [patent_app_type] => utility [patent_app_number] => 16/806063 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 15704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806063
Shared pointer for local history records used by prediction circuitry Mar 1, 2020 Issued
Array ( [id] => 16285265 [patent_doc_number] => 20200278867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => DEVICE, PROCESSOR, AND METHOD FOR SPLITTING INSTRUCTIONS AND REGISTER RENAMING [patent_app_type] => utility [patent_app_number] => 16/802341 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802341 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802341
DEVICE, PROCESSOR, AND METHOD FOR SPLITTING INSTRUCTIONS AND REGISTER RENAMING Feb 25, 2020 Abandoned
Array ( [id] => 16470253 [patent_doc_number] => 20200371790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => Method of Storing Register Data Elements to Interleave with Data Elements of a Different Register, a Processor Thereof, and a System Thereof [patent_app_type] => utility [patent_app_number] => 16/786457 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786457 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786457
Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof Feb 9, 2020 Issued
Array ( [id] => 16993976 [patent_doc_number] => 20210232396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => APPARATUS AND METHOD FOR INHIBITING INSTRUCTION MANIPULATION [patent_app_type] => utility [patent_app_number] => 16/773059 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773059
Apparatus and method for inhibiting instruction manipulation Jan 26, 2020 Issued
Menu