Search

Seungsook Ham

Supervisory Patent Examiner (ID: 8740, Phone: (571)272-2405 , Office: P/2800 )

Most Active Art Unit
2817
Art Unit(s)
2878, 4154, 2800, 2817
Total Applications
630
Issued Applications
510
Pending Applications
27
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17209431 [patent_doc_number] => 11169803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Computing device and method [patent_app_type] => utility [patent_app_number] => 16/714899 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 27694 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714899
Computing device and method Dec 15, 2019 Issued
Array ( [id] => 16454626 [patent_doc_number] => 20200364052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => BRANCH PENALTY REDUCTION USING MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/679412 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679412
BRANCH PENALTY REDUCTION USING MEMORY CIRCUIT Nov 10, 2019 Abandoned
Array ( [id] => 15412845 [patent_doc_number] => 20200026745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR [patent_app_type] => utility [patent_app_number] => 16/586114 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586114 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586114
APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR Sep 26, 2019 Abandoned
Array ( [id] => 16729725 [patent_doc_number] => 20210096872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => HARDWARE FOR ELIDING SECURITY CHECKS WHEN DEEMED SAFE DURING SPECULATIVE EXECUTION [patent_app_type] => utility [patent_app_number] => 16/585964 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585964 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585964
HARDWARE FOR ELIDING SECURITY CHECKS WHEN DEEMED SAFE DURING SPECULATIVE EXECUTION Sep 26, 2019 Abandoned
Array ( [id] => 18104179 [patent_doc_number] => 11544065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Bit width reconfiguration using a shadow-latch configured register file [patent_app_type] => utility [patent_app_number] => 16/585817 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5200 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585817
Bit width reconfiguration using a shadow-latch configured register file Sep 26, 2019 Issued
Array ( [id] => 17454783 [patent_doc_number] => 11269642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor [patent_app_type] => utility [patent_app_number] => 16/577264 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 15477 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577264
Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor Sep 19, 2019 Issued
Array ( [id] => 18547004 [patent_doc_number] => 11720356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Range checking instruction for setting a status value indicative of whether a first address and second address identified by the instruction correspond to the same memory attribute entry [patent_app_type] => utility [patent_app_number] => 17/271373 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 17352 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17271373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/271373
Range checking instruction for setting a status value indicative of whether a first address and second address identified by the instruction correspond to the same memory attribute entry Aug 19, 2019 Issued
Array ( [id] => 16623470 [patent_doc_number] => 20210042123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Reducing Operations of Sum-Of-Multiply-Accumulate (SOMAC) Instructions [patent_app_type] => utility [patent_app_number] => 16/535309 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16535309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/535309
Reducing operations of sum-of-multiply-accumulate (SOMAC) instructions Aug 7, 2019 Issued
Array ( [id] => 16623458 [patent_doc_number] => 20210042111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => EFFICIENT ENCODING OF HIGH FANOUT COMMUNICATIONS [patent_app_type] => utility [patent_app_number] => 16/532535 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/532535
EFFICIENT ENCODING OF HIGH FANOUT COMMUNICATIONS Aug 5, 2019 Abandoned
Array ( [id] => 18015083 [patent_doc_number] => 11507379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Managing load and store instructions for memory barrier handling [patent_app_type] => utility [patent_app_number] => 16/427678 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4749 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427678
Managing load and store instructions for memory barrier handling May 30, 2019 Issued
Array ( [id] => 15997915 [patent_doc_number] => 20200174828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => Gateway Pull Model [patent_app_type] => utility [patent_app_number] => 16/428846 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428846
Gateway pull model May 30, 2019 Issued
Array ( [id] => 16486155 [patent_doc_number] => 20200379760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => LOAD INSTRUCTION WITH TIMEOUT [patent_app_type] => utility [patent_app_number] => 16/423713 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423713
LOAD INSTRUCTION WITH TIMEOUT May 27, 2019 Abandoned
Array ( [id] => 16470265 [patent_doc_number] => 20200371802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => VECTOR INDEX REGISTERS [patent_app_type] => utility [patent_app_number] => 16/417500 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417500
Vector index registers May 19, 2019 Issued
Array ( [id] => 16470273 [patent_doc_number] => 20200371810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => INSTRUCTION SCHEDULING DURING EXECUTION IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/416581 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416581
Instruction scheduling during execution in a processor May 19, 2019 Issued
Array ( [id] => 16454629 [patent_doc_number] => 20200364055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => EFFICIENT LOAD VALUE PREDICTION [patent_app_type] => utility [patent_app_number] => 16/414415 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414415
Efficient load value prediction May 15, 2019 Issued
Array ( [id] => 17557980 [patent_doc_number] => 11314686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Hardware for supporting time triggered load anticipation in the context of a real time OS [patent_app_type] => utility [patent_app_number] => 16/412746 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412746
Hardware for supporting time triggered load anticipation in the context of a real time OS May 14, 2019 Issued
Array ( [id] => 16454624 [patent_doc_number] => 20200364050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => PROGRAM CODE COMPRESSION AND DECOMPRESSION USING MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/412968 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412968
Memory circuit for halting a program counter while fetching an instruction sequence from memory May 14, 2019 Issued
Array ( [id] => 17394761 [patent_doc_number] => 11243775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => System, apparatus and method for program order queue (POQ) to manage data dependencies in processor having multiple instruction queues [patent_app_type] => utility [patent_app_number] => 16/364688 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 13449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364688
System, apparatus and method for program order queue (POQ) to manage data dependencies in processor having multiple instruction queues Mar 25, 2019 Issued
Array ( [id] => 16116349 [patent_doc_number] => 20200210197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SECURE PREDICTORS FOR SPECULATIVE EXECUTION [patent_app_type] => utility [patent_app_number] => 16/362121 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362121
Secure predictors for speculative execution Mar 21, 2019 Issued
Array ( [id] => 17744467 [patent_doc_number] => 11392537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Reach-based explicit dataflow processors, and related computer-readable media and methods [patent_app_type] => utility [patent_app_number] => 16/356875 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10108 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356875
Reach-based explicit dataflow processors, and related computer-readable media and methods Mar 17, 2019 Issued
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