
Shaka Shakar White
Examiner (ID: 4923)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2826, 2829, 2809, 2823 |
| Total Applications | 474 |
| Issued Applications | 353 |
| Pending Applications | 0 |
| Abandoned Applications | 121 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5944276
[patent_doc_number] => 20110104896
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-05
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/903522
[patent_app_country] => US
[patent_app_date] => 2010-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14283
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20110104896.pdf
[firstpage_image] =>[orig_patent_app_number] => 12903522
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/903522 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS | Oct 12, 2010 | Abandoned |
Array
(
[id] => 6047813
[patent_doc_number] => 20110207334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/902212
[patent_app_country] => US
[patent_app_date] => 2010-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2520
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20110207334.pdf
[firstpage_image] =>[orig_patent_app_number] => 12902212
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/902212 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Oct 11, 2010 | Abandoned |
Array
(
[id] => 4608886
[patent_doc_number] => 07994025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Wafer processing method without occurrence of damage to device area'
[patent_app_type] => utility
[patent_app_number] => 12/902311
[patent_app_country] => US
[patent_app_date] => 2010-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2542
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/994/07994025.pdf
[firstpage_image] =>[orig_patent_app_number] => 12902311
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/902311 | Wafer processing method without occurrence of damage to device area | Oct 11, 2010 | Issued |
Array
(
[id] => 8127593
[patent_doc_number] => 20120088345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'METHOD OF FORMING SILICIDE FOR CONTACT PLUGS'
[patent_app_type] => utility
[patent_app_number] => 12/902149
[patent_app_country] => US
[patent_app_date] => 2010-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4161
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20120088345.pdf
[firstpage_image] =>[orig_patent_app_number] => 12902149
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/902149 | METHOD OF FORMING SILICIDE FOR CONTACT PLUGS | Oct 11, 2010 | Abandoned |
Array
(
[id] => 7762150
[patent_doc_number] => 08114757
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-02-14
[patent_title] => 'Semiconductor device and structure'
[patent_app_type] => utility
[patent_app_number] => 12/901902
[patent_app_country] => US
[patent_app_date] => 2010-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 299
[patent_figures_cnt] => 303
[patent_no_of_words] => 30880
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/114/08114757.pdf
[firstpage_image] =>[orig_patent_app_number] => 12901902
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/901902 | Semiconductor device and structure | Oct 10, 2010 | Issued |
Array
(
[id] => 7550631
[patent_doc_number] => 08062963
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-11-22
[patent_title] => 'Method of fabricating a semiconductor device having an epitaxy region'
[patent_app_type] => utility
[patent_app_number] => 12/900895
[patent_app_country] => US
[patent_app_date] => 2010-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3256
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/062/08062963.pdf
[firstpage_image] =>[orig_patent_app_number] => 12900895
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/900895 | Method of fabricating a semiconductor device having an epitaxy region | Oct 7, 2010 | Issued |
Array
(
[id] => 7540266
[patent_doc_number] => 08058109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-15
[patent_title] => 'Method for manufacturing a semiconductor structure'
[patent_app_type] => utility
[patent_app_number] => 12/899530
[patent_app_country] => US
[patent_app_date] => 2010-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3653
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/058/08058109.pdf
[firstpage_image] =>[orig_patent_app_number] => 12899530
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/899530 | Method for manufacturing a semiconductor structure | Oct 5, 2010 | Issued |
Array
(
[id] => 6055231
[patent_doc_number] => 20110111591
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-12
[patent_title] => 'Semiconductor Wafer Having Through-Hole Vias on Saw Streets With Backside Redistribution Layer'
[patent_app_type] => utility
[patent_app_number] => 12/896430
[patent_app_country] => US
[patent_app_date] => 2010-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4531
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20110111591.pdf
[firstpage_image] =>[orig_patent_app_number] => 12896430
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/896430 | Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer | Sep 30, 2010 | Issued |
Array
(
[id] => 8664346
[patent_doc_number] => 08377807
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-19
[patent_title] => 'Method for minimizing defects in a semiconductor substrate due to ion implantation'
[patent_app_type] => utility
[patent_app_number] => 12/895657
[patent_app_country] => US
[patent_app_date] => 2010-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2344
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895657
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/895657 | Method for minimizing defects in a semiconductor substrate due to ion implantation | Sep 29, 2010 | Issued |
Array
(
[id] => 8664322
[patent_doc_number] => 08377783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-19
[patent_title] => 'Method for reducing punch-through in a transistor device'
[patent_app_type] => utility
[patent_app_number] => 12/895695
[patent_app_country] => US
[patent_app_date] => 2010-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1481
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895695
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/895695 | Method for reducing punch-through in a transistor device | Sep 29, 2010 | Issued |
Array
(
[id] => 8301549
[patent_doc_number] => 20120184107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-19
[patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/498259
[patent_app_country] => US
[patent_app_date] => 2010-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 13084
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13498259
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/498259 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD | Sep 28, 2010 | Abandoned |
Array
(
[id] => 9823403
[patent_doc_number] => 08932887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'Method for manufacturing LED with transparent ceramics'
[patent_app_type] => utility
[patent_app_number] => 13/497824
[patent_app_country] => US
[patent_app_date] => 2010-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3744
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13497824
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/497824 | Method for manufacturing LED with transparent ceramics | Sep 28, 2010 | Issued |
Array
(
[id] => 8214901
[patent_doc_number] => 08193587
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-05
[patent_title] => 'Manufacturing method of semiconductor device, manufacturing method of display device, semiconductor device, display device, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 12/881480
[patent_app_country] => US
[patent_app_date] => 2010-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 42
[patent_no_of_words] => 16680
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/193/08193587.pdf
[firstpage_image] =>[orig_patent_app_number] => 12881480
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/881480 | Manufacturing method of semiconductor device, manufacturing method of display device, semiconductor device, display device, and electronic device | Sep 13, 2010 | Issued |
Array
(
[id] => 6624665
[patent_doc_number] => 20100311238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-09
[patent_title] => 'METHOD OF FORMING COPPER WIRING LAYER'
[patent_app_type] => utility
[patent_app_number] => 12/859018
[patent_app_country] => US
[patent_app_date] => 2010-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10943
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0311/20100311238.pdf
[firstpage_image] =>[orig_patent_app_number] => 12859018
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/859018 | METHOD OF FORMING COPPER WIRING LAYER | Aug 17, 2010 | Abandoned |
Array
(
[id] => 5944223
[patent_doc_number] => 20110104843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-05
[patent_title] => 'METHOD OF REDUCING DEGRADATION OF MULTI QUANTUM WELL (MQW) LIGHT EMITTING DIODES'
[patent_app_type] => utility
[patent_app_number] => 12/842908
[patent_app_country] => US
[patent_app_date] => 2010-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8727
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20110104843.pdf
[firstpage_image] =>[orig_patent_app_number] => 12842908
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/842908 | METHOD OF REDUCING DEGRADATION OF MULTI QUANTUM WELL (MQW) LIGHT EMITTING DIODES | Jul 22, 2010 | Abandoned |
Array
(
[id] => 6082070
[patent_doc_number] => 20110143512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-16
[patent_title] => 'METHOD FOR DUAL ENERGY IMPLANTATION FOR ULTRA-SHALLOW JUNCTION FORMATION OF MOS DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/830241
[patent_app_country] => US
[patent_app_date] => 2010-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4013
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20110143512.pdf
[firstpage_image] =>[orig_patent_app_number] => 12830241
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/830241 | Method for dual energy implantation for ultra-shallow junction formation of MOS devices | Jul 1, 2010 | Issued |
Array
(
[id] => 6231365
[patent_doc_number] => 20100264550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-21
[patent_title] => 'SELF-ALIGNED CONTACT'
[patent_app_type] => utility
[patent_app_number] => 12/825515
[patent_app_country] => US
[patent_app_date] => 2010-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4338
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20100264550.pdf
[firstpage_image] =>[orig_patent_app_number] => 12825515
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/825515 | Self-aligned contact set | Jun 28, 2010 | Issued |
Array
(
[id] => 6520794
[patent_doc_number] => 20100269595
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-28
[patent_title] => 'INTEGRATED DIFFERENTIAL PRESSURE SENSOR'
[patent_app_type] => utility
[patent_app_number] => 12/826388
[patent_app_country] => US
[patent_app_date] => 2010-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4200
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0269/20100269595.pdf
[firstpage_image] =>[orig_patent_app_number] => 12826388
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/826388 | Integrated differential pressure sensor | Jun 28, 2010 | Issued |
Array
(
[id] => 6273877
[patent_doc_number] => 20100255666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'THERMAL PROCESSING METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/819337
[patent_app_country] => US
[patent_app_date] => 2010-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2643
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0255/20100255666.pdf
[firstpage_image] =>[orig_patent_app_number] => 12819337
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/819337 | THERMAL PROCESSING METHOD | Jun 20, 2010 | Abandoned |
Array
(
[id] => 8310472
[patent_doc_number] => 20120187498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-26
[patent_title] => 'Field-Effect Transistor with Integrated TJBS Diode'
[patent_app_type] => utility
[patent_app_number] => 13/388738
[patent_app_country] => US
[patent_app_date] => 2010-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2364
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13388738
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/388738 | Field-Effect Transistor with Integrated TJBS Diode | Jun 9, 2010 | Abandoned |