
Shaka Shakar White
Examiner (ID: 4923)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2826, 2829, 2809, 2823 |
| Total Applications | 474 |
| Issued Applications | 353 |
| Pending Applications | 0 |
| Abandoned Applications | 121 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5120113
[patent_doc_number] => 20070141827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'METHOD FOR FORMING COPPER LINE'
[patent_app_type] => utility
[patent_app_number] => 11/609874
[patent_app_country] => US
[patent_app_date] => 2006-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2520
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20070141827.pdf
[firstpage_image] =>[orig_patent_app_number] => 11609874
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/609874 | METHOD FOR FORMING COPPER LINE | Dec 11, 2006 | Abandoned |
Array
(
[id] => 168078
[patent_doc_number] => 07666689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'Method to remove circuit patterns from a wafer'
[patent_app_type] => utility
[patent_app_number] => 11/609573
[patent_app_country] => US
[patent_app_date] => 2006-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1397
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/666/07666689.pdf
[firstpage_image] =>[orig_patent_app_number] => 11609573
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/609573 | Method to remove circuit patterns from a wafer | Dec 11, 2006 | Issued |
Array
(
[id] => 4782709
[patent_doc_number] => 20080136038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'INTEGRATED CIRCUITS WITH CONDUCTIVE FEATURES IN THROUGH HOLES PASSING THROUGH OTHER CONDUCTIVE FEATURES AND THROUGH A SEMICONDUCTOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/567494
[patent_app_country] => US
[patent_app_date] => 2006-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3306
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20080136038.pdf
[firstpage_image] =>[orig_patent_app_number] => 11567494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/567494 | INTEGRATED CIRCUITS WITH CONDUCTIVE FEATURES IN THROUGH HOLES PASSING THROUGH OTHER CONDUCTIVE FEATURES AND THROUGH A SEMICONDUCTOR SUBSTRATE | Dec 5, 2006 | Abandoned |
Array
(
[id] => 359596
[patent_doc_number] => 07485475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Method of accelerating test of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/561293
[patent_app_country] => US
[patent_app_date] => 2006-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 21
[patent_no_of_words] => 7031
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/485/07485475.pdf
[firstpage_image] =>[orig_patent_app_number] => 11561293
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/561293 | Method of accelerating test of semiconductor device | Nov 16, 2006 | Issued |
Array
(
[id] => 191338
[patent_doc_number] => 07642651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Multi-layer interconnect with isolation layer'
[patent_app_type] => utility
[patent_app_number] => 11/560504
[patent_app_country] => US
[patent_app_date] => 2006-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3797
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/642/07642651.pdf
[firstpage_image] =>[orig_patent_app_number] => 11560504
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/560504 | Multi-layer interconnect with isolation layer | Nov 15, 2006 | Issued |
Array
(
[id] => 163255
[patent_doc_number] => 07671461
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method and system for hermetically sealing packages for optics'
[patent_app_type] => utility
[patent_app_number] => 11/560784
[patent_app_country] => US
[patent_app_date] => 2006-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 5493
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/671/07671461.pdf
[firstpage_image] =>[orig_patent_app_number] => 11560784
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/560784 | Method and system for hermetically sealing packages for optics | Nov 15, 2006 | Issued |
Array
(
[id] => 5120043
[patent_doc_number] => 20070141757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Method of manufacturing flexible wiring substrate and method of manufacturing electronic component mounting structure'
[patent_app_type] => utility
[patent_app_number] => 11/600104
[patent_app_country] => US
[patent_app_date] => 2006-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5278
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20070141757.pdf
[firstpage_image] =>[orig_patent_app_number] => 11600104
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/600104 | Method of manufacturing flexible wiring substrate and method of manufacturing electronic component mounting structure | Nov 15, 2006 | Abandoned |
Array
(
[id] => 4901788
[patent_doc_number] => 20080111200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'FORMING CONDUCTIVE STUD FOR SEMICONDUCTIVE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 11/559574
[patent_app_country] => US
[patent_app_date] => 2006-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5618
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20080111200.pdf
[firstpage_image] =>[orig_patent_app_number] => 11559574
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559574 | Forming conductive stud for semiconductive devices | Nov 13, 2006 | Issued |
Array
(
[id] => 303527
[patent_doc_number] => 07534663
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-19
[patent_title] => 'Method for manufacturing a surface mount device'
[patent_app_type] => utility
[patent_app_number] => 11/557163
[patent_app_country] => US
[patent_app_date] => 2006-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 19
[patent_no_of_words] => 5765
[patent_no_of_claims] => 24
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/534/07534663.pdf
[firstpage_image] =>[orig_patent_app_number] => 11557163
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/557163 | Method for manufacturing a surface mount device | Nov 6, 2006 | Issued |
Array
(
[id] => 4893495
[patent_doc_number] => 20080102593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/553704
[patent_app_country] => US
[patent_app_date] => 2006-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5398
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20080102593.pdf
[firstpage_image] =>[orig_patent_app_number] => 11553704
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/553704 | Method for fabricating a semiconductor structure | Oct 26, 2006 | Issued |
Array
(
[id] => 817062
[patent_doc_number] => 07410870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-12
[patent_title] => 'Methods of forming non-volatile memory devices and devices formed thereby'
[patent_app_type] => utility
[patent_app_number] => 11/551903
[patent_app_country] => US
[patent_app_date] => 2006-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/410/07410870.pdf
[firstpage_image] =>[orig_patent_app_number] => 11551903
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/551903 | Methods of forming non-volatile memory devices and devices formed thereby | Oct 22, 2006 | Issued |
Array
(
[id] => 4965392
[patent_doc_number] => 20080108212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'HIGH VOLTAGE VERTICALLY ORIENTED EEPROM DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/550964
[patent_app_country] => US
[patent_app_date] => 2006-10-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0108/20080108212.pdf
[firstpage_image] =>[orig_patent_app_number] => 11550964
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/550964 | HIGH VOLTAGE VERTICALLY ORIENTED EEPROM DEVICE | Oct 18, 2006 | Abandoned |
Array
(
[id] => 5101343
[patent_doc_number] => 20070184605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Method of manufacturing flash memory device'
[patent_app_type] => utility
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[patent_app_country] => US
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[pdf_file] => publications/A1/0184/20070184605.pdf
[firstpage_image] =>[orig_patent_app_number] => 11583753
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/583753 | Method of manufacturing flash memory device | Oct 17, 2006 | Issued |
Array
(
[id] => 5033493
[patent_doc_number] => 20070098032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'POLARIZATION CONTROL IN VERTICAL CAVITY SURFACE EMITTING LASERS USING OFF-AXIS EPITAXY'
[patent_app_type] => utility
[patent_app_number] => 11/549516
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0098/20070098032.pdf
[firstpage_image] =>[orig_patent_app_number] => 11549516
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/549516 | POLARIZATION CONTROL IN VERTICAL CAVITY SURFACE EMITTING LASERS USING OFF-AXIS EPITAXY | Oct 12, 2006 | Abandoned |
Array
(
[id] => 295988
[patent_doc_number] => 07541257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-02
[patent_title] => 'Semiconductor device having three-dimensional construction and method for manufacturing the same'
[patent_app_type] => utility
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[pdf_file] => patents/07/541/07541257.pdf
[firstpage_image] =>[orig_patent_app_number] => 11519064
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/519064 | Semiconductor device having three-dimensional construction and method for manufacturing the same | Sep 11, 2006 | Issued |
Array
(
[id] => 5010909
[patent_doc_number] => 20070281388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'SELECTIVE METAL SURFACE TREATMENT PROCESS AND APPARATUS FOR CIRCUIT BOARD AND RESIST USED IN THE PROCESS'
[patent_app_type] => utility
[patent_app_number] => 11/456213
[patent_app_country] => US
[patent_app_date] => 2006-07-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0281/20070281388.pdf
[firstpage_image] =>[orig_patent_app_number] => 11456213
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/456213 | SELECTIVE METAL SURFACE TREATMENT PROCESS AND APPARATUS FOR CIRCUIT BOARD AND RESIST USED IN THE PROCESS | Jul 9, 2006 | Abandoned |
Array
(
[id] => 5205189
[patent_doc_number] => 20070026671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Method of forming low resistance tungsten films'
[patent_app_type] => utility
[patent_app_number] => 11/476793
[patent_app_country] => US
[patent_app_date] => 2006-06-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/476793 | Method of forming low resistance tungsten films | Jun 28, 2006 | Abandoned |
Array
(
[id] => 4803173
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[patent_title] => 'Decreasing the etch rate of silicon nitride by carbon addition'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/478273 | Decreasing the etch rate of silicon nitride by carbon addition | Jun 28, 2006 | Issued |
Array
(
[id] => 4803151
[patent_doc_number] => 20080014739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability'
[patent_app_type] => utility
[patent_app_number] => 11/475924
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0014/20080014739.pdf
[firstpage_image] =>[orig_patent_app_number] => 11475924
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/475924 | Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability | Jun 27, 2006 | Abandoned |
Array
(
[id] => 281688
[patent_doc_number] => 07553687
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Dual seed semiconductor photodetectors'
[patent_app_type] => utility
[patent_app_number] => 11/477723
[patent_app_country] => US
[patent_app_date] => 2006-06-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/553/07553687.pdf
[firstpage_image] =>[orig_patent_app_number] => 11477723
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/477723 | Dual seed semiconductor photodetectors | Jun 27, 2006 | Issued |