Search

Shaka Shakar White

Examiner (ID: 4923)

Most Active Art Unit
2823
Art Unit(s)
2826, 2829, 2809, 2823
Total Applications
474
Issued Applications
353
Pending Applications
0
Abandoned Applications
121

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 274173 [patent_doc_number] => 07560337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Programmable resistive RAM and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/426213 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560337.pdf [firstpage_image] =>[orig_patent_app_number] => 11426213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426213
Programmable resistive RAM and manufacturing method Jun 22, 2006 Issued
Array ( [id] => 5154527 [patent_doc_number] => 20070037410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'METHOD FOR FORMING A LITHOGRAPHY PATTERN' [patent_app_type] => utility [patent_app_number] => 11/426233 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4789 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037410.pdf [firstpage_image] =>[orig_patent_app_number] => 11426233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426233
Method for forming a lithography pattern Jun 22, 2006 Issued
Array ( [id] => 5199206 [patent_doc_number] => 20070298524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHODS OF QUANTIFYING VARIATIONS RESULTING FROM MANUFACTURING-INDUCED CORNER ROUNDING OF VARIOUS FEATURES, AND STRUCTURES FOR TESTING SAME' [patent_app_type] => utility [patent_app_number] => 11/425913 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298524.pdf [firstpage_image] =>[orig_patent_app_number] => 11425913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425913
Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same Jun 21, 2006 Issued
Array ( [id] => 5477681 [patent_doc_number] => 20090200638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'MIM CAPACITOR INTEGRATION' [patent_app_type] => utility [patent_app_number] => 12/304194 [patent_app_country] => US [patent_app_date] => 2006-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4344 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20090200638.pdf [firstpage_image] =>[orig_patent_app_number] => 12304194 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/304194
MIM capacitor integration Jun 14, 2006 Issued
Array ( [id] => 102483 [patent_doc_number] => 07723224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Microelectronic assembly with back side metallization and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/453763 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723224.pdf [firstpage_image] =>[orig_patent_app_number] => 11453763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453763
Microelectronic assembly with back side metallization and method for forming the same Jun 13, 2006 Issued
Array ( [id] => 5602450 [patent_doc_number] => 20060292795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Method of manufacturing a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/449848 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292795.pdf [firstpage_image] =>[orig_patent_app_number] => 11449848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/449848
Method of manufacturing a flash memory device Jun 8, 2006 Issued
Array ( [id] => 5107135 [patent_doc_number] => 20070066013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/448678 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20070066013.pdf [firstpage_image] =>[orig_patent_app_number] => 11448678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448678
Method for fabricating semiconductor device Jun 7, 2006 Issued
Array ( [id] => 274163 [patent_doc_number] => 07560327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Method of fabricating semiconductor device with dual gate structure' [patent_app_type] => utility [patent_app_number] => 11/450658 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3377 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560327.pdf [firstpage_image] =>[orig_patent_app_number] => 11450658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450658
Method of fabricating semiconductor device with dual gate structure Jun 7, 2006 Issued
Array ( [id] => 62734 [patent_doc_number] => 07763487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Integrated differential pressure sensor and manufacturing process thereof' [patent_app_type] => utility [patent_app_number] => 11/417683 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4349 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763487.pdf [firstpage_image] =>[orig_patent_app_number] => 11417683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/417683
Integrated differential pressure sensor and manufacturing process thereof May 3, 2006 Issued
Array ( [id] => 5123547 [patent_doc_number] => 20070235817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Write margin improvement for SRAM cells with SiGe stressors' [patent_app_type] => utility [patent_app_number] => 11/401204 [patent_app_country] => US [patent_app_date] => 2006-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3220 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235817.pdf [firstpage_image] =>[orig_patent_app_number] => 11401204 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401204
Write margin improvement for SRAM cells with SiGe stressors Apr 9, 2006 Issued
Array ( [id] => 4068 [patent_doc_number] => 07816203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-19 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/378464 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3198 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816203.pdf [firstpage_image] =>[orig_patent_app_number] => 11378464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378464
Method for fabricating a semiconductor device Mar 15, 2006 Issued
Array ( [id] => 5619551 [patent_doc_number] => 20060189085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method of forming dual polysilicon gate of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/356998 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20060189085.pdf [firstpage_image] =>[orig_patent_app_number] => 11356998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356998
Method of forming dual polysilicon gate of semiconductor device Feb 16, 2006 Abandoned
Array ( [id] => 5785552 [patent_doc_number] => 20060205122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Method for fabricating a field stop zone' [patent_app_type] => utility [patent_app_number] => 11/357904 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2496 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205122.pdf [firstpage_image] =>[orig_patent_app_number] => 11357904 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357904
Method for fabricating a field stop zone Feb 16, 2006 Abandoned
Array ( [id] => 5625471 [patent_doc_number] => 20060263976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Semiconductor device with capacitor structure for improving area utilization' [patent_app_type] => utility [patent_app_number] => 11/353923 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1366 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20060263976.pdf [firstpage_image] =>[orig_patent_app_number] => 11353923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353923
Semiconductor device with capacitor structure for improving area utilization Feb 13, 2006 Abandoned
Array ( [id] => 5205096 [patent_doc_number] => 20070026578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method for forming a silicided gate' [patent_app_type] => utility [patent_app_number] => 11/354748 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2208 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026578.pdf [firstpage_image] =>[orig_patent_app_number] => 11354748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354748
Method for forming a silicided gate Feb 13, 2006 Issued
Array ( [id] => 5101338 [patent_doc_number] => 20070184600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Stressed-channel CMOS transistors' [patent_app_type] => utility [patent_app_number] => 11/348034 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184600.pdf [firstpage_image] =>[orig_patent_app_number] => 11348034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348034
Stressed-channel CMOS transistors Feb 5, 2006 Abandoned
Array ( [id] => 5672652 [patent_doc_number] => 20060178007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Method of forming copper wiring layer' [patent_app_type] => utility [patent_app_number] => 11/344014 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10937 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20060178007.pdf [firstpage_image] =>[orig_patent_app_number] => 11344014 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/344014
Method of forming copper wiring layer Jan 31, 2006 Abandoned
Array ( [id] => 151504 [patent_doc_number] => 07682981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Topography transfer method with aspect ratio scaling' [patent_app_type] => utility [patent_app_number] => 11/341953 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2291 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/682/07682981.pdf [firstpage_image] =>[orig_patent_app_number] => 11341953 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341953
Topography transfer method with aspect ratio scaling Jan 26, 2006 Issued
Array ( [id] => 270445 [patent_doc_number] => 07563681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Double-gated non-volatile memory and methods for forming thereof' [patent_app_type] => utility [patent_app_number] => 11/341973 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4253 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563681.pdf [firstpage_image] =>[orig_patent_app_number] => 11341973 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341973
Double-gated non-volatile memory and methods for forming thereof Jan 26, 2006 Issued
Array ( [id] => 330427 [patent_doc_number] => 07510922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Spacer T-gate structure for CoSi2 extendibility' [patent_app_type] => utility [patent_app_number] => 11/339953 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/510/07510922.pdf [firstpage_image] =>[orig_patent_app_number] => 11339953 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339953
Spacer T-gate structure for CoSi2 extendibility Jan 25, 2006 Issued
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