Search

Shane M Thomas

Examiner (ID: 15845, Phone: (571)272-4188 , Office: P/3903 )

Most Active Art Unit
3903
Art Unit(s)
3903, 2186
Total Applications
32042
Issued Applications
205
Pending Applications
30443
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 965669 [patent_doc_number] => 06950908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Speculative cache memory control method and multi-processor system' [patent_app_type] => utility [patent_app_number] => 10/191401 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950908.pdf [firstpage_image] =>[orig_patent_app_number] => 10191401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191401
Speculative cache memory control method and multi-processor system Jul 9, 2002 Issued
Array ( [id] => 6707613 [patent_doc_number] => 20030154347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Methods and apparatus for reducing processor power consumption' [patent_app_type] => new [patent_app_number] => 10/192599 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4923 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154347.pdf [firstpage_image] =>[orig_patent_app_number] => 10192599 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192599
Methods and apparatus for reducing processor power consumption Jul 9, 2002 Abandoned
Array ( [id] => 6661058 [patent_doc_number] => 20030135702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Microcomputer for accessing a replacing block area preset in a nonvolatile memory in place of a replaced block area accessed in the nonvolatile memory' [patent_app_type] => new [patent_app_number] => 10/191315 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12509 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135702.pdf [firstpage_image] =>[orig_patent_app_number] => 10191315 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191315
Microcomputer for accessing a replacing block area preset in a nonvolatile memory in place of a replaced block area accessed in the nonvolatile memory Jul 9, 2002 Abandoned
Array ( [id] => 1085025 [patent_doc_number] => 06834329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Cache control method and cache apparatus' [patent_app_type] => B2 [patent_app_number] => 10/190815 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12914 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834329.pdf [firstpage_image] =>[orig_patent_app_number] => 10190815 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190815
Cache control method and cache apparatus Jul 8, 2002 Issued
Array ( [id] => 629790 [patent_doc_number] => 07136960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Hardware hashing of an input of a content addressable memory (CAM) to emulate a wider CAM' [patent_app_type] => utility [patent_app_number] => 10/173516 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5889 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136960.pdf [firstpage_image] =>[orig_patent_app_number] => 10173516 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173516
Hardware hashing of an input of a content addressable memory (CAM) to emulate a wider CAM Jun 13, 2002 Issued
Array ( [id] => 6805780 [patent_doc_number] => 20030233174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Method and system for providing a location of a data interface' [patent_app_type] => new [patent_app_number] => 10/173331 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4176 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20030233174.pdf [firstpage_image] =>[orig_patent_app_number] => 10173331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173331
Method and system for providing a location of a data interface Jun 13, 2002 Issued
Array ( [id] => 6836093 [patent_doc_number] => 20030163639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Sequential command processing mode in a disc drive using command queuing' [patent_app_type] => new [patent_app_number] => 10/172528 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7998 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163639.pdf [firstpage_image] =>[orig_patent_app_number] => 10172528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172528
Sequential command processing mode in a disc drive using command queuing Jun 13, 2002 Abandoned
Array ( [id] => 1181074 [patent_doc_number] => 06754790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method of accessing memory of de-interleaving unit' [patent_app_type] => B2 [patent_app_number] => 10/173234 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3471 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754790.pdf [firstpage_image] =>[orig_patent_app_number] => 10173234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173234
Method of accessing memory of de-interleaving unit Jun 13, 2002 Issued
Array ( [id] => 6335929 [patent_doc_number] => 20020199080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Combined logic function for address limit checking' [patent_app_type] => new [patent_app_number] => 10/172116 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2677 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20020199080.pdf [firstpage_image] =>[orig_patent_app_number] => 10172116 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172116
Combined logic function for address limit checking Jun 13, 2002 Issued
Array ( [id] => 1180975 [patent_doc_number] => 06754775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for facilitating flow control during accesses to cache memory' [patent_app_type] => B2 [patent_app_number] => 10/161794 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754775.pdf [firstpage_image] =>[orig_patent_app_number] => 10161794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161794
Method and apparatus for facilitating flow control during accesses to cache memory Jun 3, 2002 Issued
Array ( [id] => 6703093 [patent_doc_number] => 20030225973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Two area stack' [patent_app_type] => new [patent_app_number] => 10/161872 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3115 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20030225973.pdf [firstpage_image] =>[orig_patent_app_number] => 10161872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161872
Two area stack Jun 3, 2002 Issued
Array ( [id] => 1109808 [patent_doc_number] => 06813700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Reduction of bus switching activity using an encoder and decoder' [patent_app_type] => B2 [patent_app_number] => 10/162010 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7031 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813700.pdf [firstpage_image] =>[orig_patent_app_number] => 10162010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162010
Reduction of bus switching activity using an encoder and decoder Jun 2, 2002 Issued
Array ( [id] => 6703081 [patent_doc_number] => 20030225961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Flash memory management system and method' [patent_app_type] => new [patent_app_number] => 10/161373 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4158 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20030225961.pdf [firstpage_image] =>[orig_patent_app_number] => 10161373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161373
Flash memory management system and method utilizing multiple block list windows Jun 2, 2002 Issued
Array ( [id] => 962182 [patent_doc_number] => 06952753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Device driver with improved timeout performance' [patent_app_type] => utility [patent_app_number] => 10/160916 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6221 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952753.pdf [firstpage_image] =>[orig_patent_app_number] => 10160916 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/160916
Device driver with improved timeout performance Jun 2, 2002 Issued
Array ( [id] => 6871541 [patent_doc_number] => 20030084231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Nonvolatile semiconductor storage device with interface functions' [patent_app_type] => new [patent_app_number] => 10/137330 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5789 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084231.pdf [firstpage_image] =>[orig_patent_app_number] => 10137330 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137330
Nonvolatile semiconductor storage device with interface functions May 2, 2002 Abandoned
Array ( [id] => 6814975 [patent_doc_number] => 20030074525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Cache control program and computer for performing cache processes' [patent_app_type] => new [patent_app_number] => 10/138621 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074525.pdf [firstpage_image] =>[orig_patent_app_number] => 10138621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/138621
Cache control program and computer for performing cache processes utilizing cache blocks ranked according to their order of reuse May 2, 2002 Issued
Array ( [id] => 7618453 [patent_doc_number] => 06944738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Scalable design for DDR SDRAM buses' [patent_app_type] => utility [patent_app_number] => 10/123398 [patent_app_country] => US [patent_app_date] => 2002-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4114 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944738.pdf [firstpage_image] =>[orig_patent_app_number] => 10123398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/123398
Scalable design for DDR SDRAM buses Apr 15, 2002 Issued
Array ( [id] => 914578 [patent_doc_number] => 07330956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Bucket based memory allocation' [patent_app_type] => utility [patent_app_number] => 10/123661 [patent_app_country] => US [patent_app_date] => 2002-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330956.pdf [firstpage_image] =>[orig_patent_app_number] => 10123661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/123661
Bucket based memory allocation Apr 15, 2002 Issued
Array ( [id] => 7678312 [patent_doc_number] => 20030196024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Apparatus and method for a skip-list based cache' [patent_app_type] => new [patent_app_number] => 10/122183 [patent_app_country] => US [patent_app_date] => 2002-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4511 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196024.pdf [firstpage_image] =>[orig_patent_app_number] => 10122183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/122183
Apparatus and method for a skip-list based cache Apr 15, 2002 Abandoned
Array ( [id] => 744968 [patent_doc_number] => 07035993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Flash memory data access method and configuration employing logical-to-virtual and virtual-to-physical sector mapping' [patent_app_type] => utility [patent_app_number] => 10/063278 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5696 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035993.pdf [firstpage_image] =>[orig_patent_app_number] => 10063278 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063278
Flash memory data access method and configuration employing logical-to-virtual and virtual-to-physical sector mapping Apr 7, 2002 Issued
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