
Shane M Thomas
Examiner (ID: 15845, Phone: (571)272-4188 , Office: P/3903 )
| Most Active Art Unit | 3903 |
| Art Unit(s) | 3903, 2186 |
| Total Applications | 32042 |
| Issued Applications | 205 |
| Pending Applications | 30443 |
| Abandoned Applications | 61 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 965669
[patent_doc_number] => 06950908
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[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'Speculative cache memory control method and multi-processor system'
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Array
(
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[patent_issue_date] => 2003-08-14
[patent_title] => 'Methods and apparatus for reducing processor power consumption'
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Array
(
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[patent_doc_number] => 20030135702
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[patent_issue_date] => 2003-07-17
[patent_title] => 'Microcomputer for accessing a replacing block area preset in a nonvolatile memory in place of a replaced block area accessed in the nonvolatile memory'
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Array
(
[id] => 1085025
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[patent_issue_date] => 2004-12-21
[patent_title] => 'Cache control method and cache apparatus'
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Array
(
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[patent_title] => 'Hardware hashing of an input of a content addressable memory (CAM) to emulate a wider CAM'
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Array
(
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Array
(
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[patent_title] => 'Sequential command processing mode in a disc drive using command queuing'
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Array
(
[id] => 1181074
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[patent_issue_date] => 2004-06-22
[patent_title] => 'Method of accessing memory of de-interleaving unit'
[patent_app_type] => B2
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172116 | Combined logic function for address limit checking | Jun 13, 2002 | Issued |
Array
(
[id] => 1180975
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[patent_issue_date] => 2004-06-22
[patent_title] => 'Method and apparatus for facilitating flow control during accesses to cache memory'
[patent_app_type] => B2
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Array
(
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[patent_title] => 'Two area stack'
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Array
(
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Array
(
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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