Search

Shane M Thomas

Examiner (ID: 15845, Phone: (571)272-4188 , Office: P/3903 )

Most Active Art Unit
3903
Art Unit(s)
3903, 2186
Total Applications
32042
Issued Applications
205
Pending Applications
30443
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4730324 [patent_doc_number] => 20080209105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Memory Controller, Control Method For Accessing Semiconductor Memory And System' [patent_app_type] => utility [patent_app_number] => 12/037541 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209105.pdf [firstpage_image] =>[orig_patent_app_number] => 12037541 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037541
Method and apparatus for controlling memory precharge operation Feb 25, 2008 Issued
Array ( [id] => 4793914 [patent_doc_number] => 20080294888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'DEPLOY TARGET COMPUTER, DEPLOYMENT SYSTEM AND DEPLOYING METHOD' [patent_app_type] => utility [patent_app_number] => 12/024337 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7466 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294888.pdf [firstpage_image] =>[orig_patent_app_number] => 12024337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024337
DEPLOY TARGET COMPUTER, DEPLOYMENT SYSTEM AND DEPLOYING METHOD Jan 31, 2008 Abandoned
Array ( [id] => 4787627 [patent_doc_number] => 20080140956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/018144 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13438 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140956.pdf [firstpage_image] =>[orig_patent_app_number] => 12018144 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018144
ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM Jan 21, 2008 Abandoned
Array ( [id] => 4616524 [patent_doc_number] => 07991977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Advanced processor translation lookaside buffer management in a multithreaded system' [patent_app_type] => utility [patent_app_number] => 11/961910 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 13461 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/991/07991977.pdf [firstpage_image] =>[orig_patent_app_number] => 11961910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961910
Advanced processor translation lookaside buffer management in a multithreaded system Dec 19, 2007 Issued
Array ( [id] => 4829864 [patent_doc_number] => 20080126709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'ADVANCED PROCESSOR WITH SYSTEM ON A CHIP INTERCONNECT TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 11/961884 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13448 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126709.pdf [firstpage_image] =>[orig_patent_app_number] => 11961884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961884
Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages Dec 19, 2007 Issued
Array ( [id] => 5548084 [patent_doc_number] => 20090157961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TWO-SIDED, DYNAMIC CACHE INJECTION CONTROL' [patent_app_type] => utility [patent_app_number] => 11/958424 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157961.pdf [firstpage_image] =>[orig_patent_app_number] => 11958424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958424
Two-sided, dynamic cache injection control Dec 17, 2007 Issued
Array ( [id] => 5548102 [patent_doc_number] => 20090157979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TARGET COMPUTER PROCESSOR UNIT (CPU) DETERMINATION DURING CACHE INJECTION USING INPUT/OUTPUT (I/O) HUB/CHIPSET RESOURCES' [patent_app_type] => utility [patent_app_number] => 11/958435 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157979.pdf [firstpage_image] =>[orig_patent_app_number] => 11958435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958435
Target computer processor unit (CPU) determination during cache injection using input/output I/O) hub/chipset resources Dec 17, 2007 Issued
Array ( [id] => 5548101 [patent_doc_number] => 20090157978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TARGET COMPUTER PROCESSOR UNIT (CPU) DETERMINATION DURING CACHE INJECTION USING INPUT/OUTPUT (I/O) ADAPTER RESOURCES' [patent_app_type] => utility [patent_app_number] => 11/958431 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157978.pdf [firstpage_image] =>[orig_patent_app_number] => 11958431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958431
Target computer processor unit (CPU) determination during cache injection using input/output (I/O) adapter resources Dec 17, 2007 Issued
Array ( [id] => 5548067 [patent_doc_number] => 20090157944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TRACKING STORE ORDERING HAZARDS IN AN OUT-OF-ORDER STORE QUEUR' [patent_app_type] => utility [patent_app_number] => 11/958328 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157944.pdf [firstpage_image] =>[orig_patent_app_number] => 11958328 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958328
Tracking store ordering hazards in an out-of-order store queue Dec 16, 2007 Issued
Array ( [id] => 4590875 [patent_doc_number] => 07827359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Clock encoded pre-fetch to access memory data in clustering network environment' [patent_app_type] => utility [patent_app_number] => 11/957027 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 25342 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827359.pdf [firstpage_image] =>[orig_patent_app_number] => 11957027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957027
Clock encoded pre-fetch to access memory data in clustering network environment Dec 13, 2007 Issued
Array ( [id] => 4636898 [patent_doc_number] => 08015361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Memory-centric page table walker' [patent_app_type] => utility [patent_app_number] => 11/956625 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2107 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015361.pdf [firstpage_image] =>[orig_patent_app_number] => 11956625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956625
Memory-centric page table walker Dec 13, 2007 Issued
Array ( [id] => 4448923 [patent_doc_number] => 07865675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Controlling cleaning of data values within a hardware accelerator' [patent_app_type] => utility [patent_app_number] => 12/000005 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4967 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865675.pdf [firstpage_image] =>[orig_patent_app_number] => 12000005 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000005
Controlling cleaning of data values within a hardware accelerator Dec 5, 2007 Issued
Array ( [id] => 4581087 [patent_doc_number] => 07840745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Data accessing system, controller and storage device having the same, and operation method thereof' [patent_app_type] => utility [patent_app_number] => 11/840678 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8496 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840745.pdf [firstpage_image] =>[orig_patent_app_number] => 11840678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840678
Data accessing system, controller and storage device having the same, and operation method thereof Aug 16, 2007 Issued
Array ( [id] => 4706322 [patent_doc_number] => 20080065846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'APPARATUS FOR FACILITATING DISASTER RECOVERY' [patent_app_type] => utility [patent_app_number] => 11/840829 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5935 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065846.pdf [firstpage_image] =>[orig_patent_app_number] => 11840829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840829
Apparatus for facilitating disaster recovery Aug 16, 2007 Issued
Array ( [id] => 4499191 [patent_doc_number] => 07904639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Modular command structure for memory and memory system' [patent_app_type] => utility [patent_app_number] => 11/840692 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 10154 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904639.pdf [firstpage_image] =>[orig_patent_app_number] => 11840692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840692
Modular command structure for memory and memory system Aug 16, 2007 Issued
Array ( [id] => 4706323 [patent_doc_number] => 20080065847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'APPARATUS FOR FACILITATING DISASTER RECOVERY' [patent_app_type] => utility [patent_app_number] => 11/840833 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5935 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065847.pdf [firstpage_image] =>[orig_patent_app_number] => 11840833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840833
APPARATUS FOR FACILITATING DISASTER RECOVERY Aug 16, 2007 Abandoned
Array ( [id] => 7694277 [patent_doc_number] => 20080120467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Information processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/878019 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5792 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20080120467.pdf [firstpage_image] =>[orig_patent_app_number] => 11878019 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/878019
Apparatus and method for generating a secondary cache index Jul 19, 2007 Issued
Array ( [id] => 5311958 [patent_doc_number] => 20090019239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Memory Controller Granular Read Queue Dynamic Optimization of Command Selection' [patent_app_type] => utility [patent_app_number] => 11/775459 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6854 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019239.pdf [firstpage_image] =>[orig_patent_app_number] => 11775459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775459
Memory controller granular read queue dynamic optimization of command selection Jul 9, 2007 Issued
Array ( [id] => 5311957 [patent_doc_number] => 20090019238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Memory Controller Read Queue Dynamic Optimization of Command Selection' [patent_app_type] => utility [patent_app_number] => 11/775411 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6853 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019238.pdf [firstpage_image] =>[orig_patent_app_number] => 11775411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775411
Memory Controller Read Queue Dynamic Optimization of Command Selection Jul 9, 2007 Abandoned
Array ( [id] => 4854493 [patent_doc_number] => 20080320236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'System having cache snoop interface independent of system bus interface' [patent_app_type] => utility [patent_app_number] => 11/767882 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320236.pdf [firstpage_image] =>[orig_patent_app_number] => 11767882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767882
System having cache snoop interface independent of system bus interface Jun 24, 2007 Abandoned
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