Search

Shane M. Thomas

Examiner (ID: 18001, Phone: (571)272-4188 , Office: P/3903 )

Most Active Art Unit
3903
Art Unit(s)
3903, 2186
Total Applications
32048
Issued Applications
205
Pending Applications
30452
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5809324 [patent_doc_number] => 20060095679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and apparatus for pushing data into a processor cache' [patent_app_type] => utility [patent_app_number] => 10/977830 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5772 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095679.pdf [firstpage_image] =>[orig_patent_app_number] => 10977830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/977830
Method and apparatus for pushing data into a processor cache Oct 27, 2004 Abandoned
Array ( [id] => 7035886 [patent_doc_number] => 20050033832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Advanced processor with use of bridges on a data movement ring for optimal redirection of memory and I/O traffic' [patent_app_type] => utility [patent_app_number] => 10/930179 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13426 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20050033832.pdf [firstpage_image] =>[orig_patent_app_number] => 10930179 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930179
Advanced processor with use of bridges on a data movement ring for optimal redirection of memory and I/O traffic Aug 30, 2004 Issued
Array ( [id] => 5725530 [patent_doc_number] => 20060056290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Advanced processor with implementation of memory ordering on a ring based data movement network' [patent_app_type] => utility [patent_app_number] => 10/930187 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13442 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20060056290.pdf [firstpage_image] =>[orig_patent_app_number] => 10930187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930187
Advanced processor with implementation of memory ordering on a ring based data movement network Aug 30, 2004 Issued
Array ( [id] => 7123734 [patent_doc_number] => 20050015563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Guaranteed undo retention' [patent_app_type] => utility [patent_app_number] => 10/920874 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5902 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20050015563.pdf [firstpage_image] =>[orig_patent_app_number] => 10920874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920874
Guaranteed undo retention Aug 16, 2004 Issued
Array ( [id] => 615744 [patent_doc_number] => 07149861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Disk array device capable of backing up and limiting access to a system logical unit' [patent_app_type] => utility [patent_app_number] => 10/911604 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 36 [patent_no_of_words] => 16538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149861.pdf [firstpage_image] =>[orig_patent_app_number] => 10911604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911604
Disk array device capable of backing up and limiting access to a system logical unit Aug 4, 2004 Issued
Array ( [id] => 7222534 [patent_doc_number] => 20050055503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Advanced processor with cache coherency' [patent_app_type] => utility [patent_app_number] => 10/897577 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055503.pdf [firstpage_image] =>[orig_patent_app_number] => 10897577 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897577
Advanced processor with cache coherency Jul 22, 2004 Issued
Array ( [id] => 7222543 [patent_doc_number] => 20050055504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Advanced processor with system on a chip interconnect technology' [patent_app_type] => utility [patent_app_number] => 10/898008 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13401 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055504.pdf [firstpage_image] =>[orig_patent_app_number] => 10898008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898008
Advanced processor with system on a chip interconnect technology Jul 22, 2004 Issued
Array ( [id] => 7222589 [patent_doc_number] => 20050055510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Advanced processor translation lookaside buffer management in a multithreaded system' [patent_app_type] => utility [patent_app_number] => 10/898150 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13432 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055510.pdf [firstpage_image] =>[orig_patent_app_number] => 10898150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898150
Advanced processor translation lookaside buffer management in a multithreaded system Jul 22, 2004 Issued
Array ( [id] => 593361 [patent_doc_number] => 07461213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Advanced processor system using request, data, snoop, and response rings' [patent_app_type] => utility [patent_app_number] => 10/897576 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 13451 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461213.pdf [firstpage_image] =>[orig_patent_app_number] => 10897576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897576
Advanced processor system using request, data, snoop, and response rings Jul 22, 2004 Issued
Array ( [id] => 615755 [patent_doc_number] => 07149867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware' [patent_app_type] => utility [patent_app_number] => 10/869200 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149867.pdf [firstpage_image] =>[orig_patent_app_number] => 10869200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869200
System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware Jun 15, 2004 Issued
Array ( [id] => 332944 [patent_doc_number] => 07512764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Method for allocating a memory of a de-interleaving unit' [patent_app_type] => utility [patent_app_number] => 10/843706 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4421 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512764.pdf [firstpage_image] =>[orig_patent_app_number] => 10843706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/843706
Method for allocating a memory of a de-interleaving unit May 9, 2004 Issued
Array ( [id] => 921995 [patent_doc_number] => 07325102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-29 [patent_title] => 'Mechanism and method for cache snoop filtering' [patent_app_type] => utility [patent_app_number] => 10/821430 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5056 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325102.pdf [firstpage_image] =>[orig_patent_app_number] => 10821430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821430
Mechanism and method for cache snoop filtering Apr 8, 2004 Issued
Array ( [id] => 7448866 [patent_doc_number] => 20040268059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Multi-node system with split ownership and access right coherence mechanism' [patent_app_type] => new [patent_app_number] => 10/821564 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 47995 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268059.pdf [firstpage_image] =>[orig_patent_app_number] => 10821564 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821564
Multi-node system with split ownership and access right coherence mechanism Apr 8, 2004 Issued
Array ( [id] => 7603627 [patent_doc_number] => 07117312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Mechanism and method employing a plurality of hash functions for cache snoop filtering' [patent_app_type] => utility [patent_app_number] => 10/821380 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117312.pdf [firstpage_image] =>[orig_patent_app_number] => 10821380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821380
Mechanism and method employing a plurality of hash functions for cache snoop filtering Apr 8, 2004 Issued
Array ( [id] => 7261978 [patent_doc_number] => 20040260886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Multi-node system with interface intervention to satisfy coherency transactions transparently to active devices' [patent_app_type] => new [patent_app_number] => 10/821557 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 48121 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260886.pdf [firstpage_image] =>[orig_patent_app_number] => 10821557 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821557
Multi-node system with interface intervention to satisfy coherency transactions transparently to active devices Apr 8, 2004 Abandoned
Array ( [id] => 806068 [patent_doc_number] => 07424570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Method for patching ROM instructions in an electronic embedded system including at least a further memory portion' [patent_app_type] => utility [patent_app_number] => 10/820462 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2209 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424570.pdf [firstpage_image] =>[orig_patent_app_number] => 10820462 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820462
Method for patching ROM instructions in an electronic embedded system including at least a further memory portion Apr 7, 2004 Issued
Array ( [id] => 5704559 [patent_doc_number] => 20060193607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method, system and software for fast archiving from hdd to optical disk drive' [patent_app_type] => utility [patent_app_number] => 10/551322 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3211 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20060193607.pdf [firstpage_image] =>[orig_patent_app_number] => 10551322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/551322
Method, system and software for fast archiving from hdd to optical disk drive Mar 21, 2004 Abandoned
Array ( [id] => 7290264 [patent_doc_number] => 20040148279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Scalable distributed hierarchical cache' [patent_app_type] => new [patent_app_number] => 10/451187 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 19099 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148279.pdf [firstpage_image] =>[orig_patent_app_number] => 10451187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/451187
Scalable distributed hierarchical cache Mar 15, 2004 Abandoned
Array ( [id] => 7177836 [patent_doc_number] => 20050204111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Command scheduling for dual-data-rate two (DDR2) memory devices' [patent_app_type] => utility [patent_app_number] => 10/798600 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204111.pdf [firstpage_image] =>[orig_patent_app_number] => 10798600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798600
Command scheduling for dual-data-rate two (DDR2) memory devices Mar 9, 2004 Abandoned
Array ( [id] => 609466 [patent_doc_number] => 07155567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Control method for data transfer device, data transfer circuit, and disk array device' [patent_app_type] => utility [patent_app_number] => 10/795996 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8479 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155567.pdf [firstpage_image] =>[orig_patent_app_number] => 10795996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/795996
Control method for data transfer device, data transfer circuit, and disk array device Mar 9, 2004 Issued
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