Search

Shane M Thomas

Examiner (ID: 15845, Phone: (571)272-4188 , Office: P/3903 )

Most Active Art Unit
3903
Art Unit(s)
3903, 2186
Total Applications
32042
Issued Applications
205
Pending Applications
30443
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7177836 [patent_doc_number] => 20050204111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Command scheduling for dual-data-rate two (DDR2) memory devices' [patent_app_type] => utility [patent_app_number] => 10/798600 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204111.pdf [firstpage_image] =>[orig_patent_app_number] => 10798600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798600
Command scheduling for dual-data-rate two (DDR2) memory devices Mar 9, 2004 Abandoned
Array ( [id] => 512976 [patent_doc_number] => 07206906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Physical address mapping framework' [patent_app_type] => utility [patent_app_number] => 10/798174 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3503 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206906.pdf [firstpage_image] =>[orig_patent_app_number] => 10798174 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798174
Physical address mapping framework Mar 9, 2004 Issued
Array ( [id] => 4486379 [patent_doc_number] => 07870346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Servo controller interface module for embedded disk controllers' [patent_app_type] => utility [patent_app_number] => 10/796727 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 57 [patent_no_of_words] => 8660 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870346.pdf [firstpage_image] =>[orig_patent_app_number] => 10796727 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796727
Servo controller interface module for embedded disk controllers Mar 8, 2004 Issued
Array ( [id] => 518446 [patent_doc_number] => 07203818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Microcontroller instruction set' [patent_app_type] => utility [patent_app_number] => 10/796771 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 97 [patent_figures_cnt] => 116 [patent_no_of_words] => 13413 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203818.pdf [firstpage_image] =>[orig_patent_app_number] => 10796771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796771
Microcontroller instruction set Mar 8, 2004 Issued
Array ( [id] => 7084914 [patent_doc_number] => 20050050294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Segmented storage system mapping' [patent_app_type] => utility [patent_app_number] => 10/778149 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2950 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050294.pdf [firstpage_image] =>[orig_patent_app_number] => 10778149 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778149
Segmented storage system mapping Feb 16, 2004 Issued
Array ( [id] => 7148846 [patent_doc_number] => 20050120175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Disk array apparatus and control method for disk array apparatus' [patent_app_type] => utility [patent_app_number] => 10/771455 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20050120175.pdf [firstpage_image] =>[orig_patent_app_number] => 10771455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/771455
Disk array apparatus and control method for disk array apparatus Feb 4, 2004 Issued
Array ( [id] => 6919790 [patent_doc_number] => 20050097272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Disk array device and control method of disk array device' [patent_app_type] => utility [patent_app_number] => 10/767444 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7269 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097272.pdf [firstpage_image] =>[orig_patent_app_number] => 10767444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767444
Disk array device with utilization of a dual-bus architecture dependent on data length of cache access requests Jan 29, 2004 Issued
Array ( [id] => 508146 [patent_doc_number] => 07210013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Data protection for computer system' [patent_app_type] => utility [patent_app_number] => 10/766340 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5358 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/210/07210013.pdf [firstpage_image] =>[orig_patent_app_number] => 10766340 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766340
Data protection for computer system Jan 27, 2004 Issued
Array ( [id] => 581745 [patent_doc_number] => 07162568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Apparatus and method for flash ROM management' [patent_app_type] => utility [patent_app_number] => 10/757464 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/162/07162568.pdf [firstpage_image] =>[orig_patent_app_number] => 10757464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757464
Apparatus and method for flash ROM management Jan 14, 2004 Issued
Array ( [id] => 7042251 [patent_doc_number] => 20050160242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Asynchronous hybrid mirroring system' [patent_app_type] => utility [patent_app_number] => 10/758484 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5620 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160242.pdf [firstpage_image] =>[orig_patent_app_number] => 10758484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/758484
Asynchronous hybrid mirroring system Jan 14, 2004 Issued
Array ( [id] => 633288 [patent_doc_number] => 07133960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-07 [patent_title] => 'Logical to physical address mapping of chip selects' [patent_app_type] => utility [patent_app_number] => 10/749464 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3390 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133960.pdf [firstpage_image] =>[orig_patent_app_number] => 10749464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749464
Logical to physical address mapping of chip selects Dec 30, 2003 Issued
Array ( [id] => 581783 [patent_doc_number] => 07159091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-02 [patent_title] => 'Dynamic relocation of execute in place applications' [patent_app_type] => utility [patent_app_number] => 10/749466 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5746 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159091.pdf [firstpage_image] =>[orig_patent_app_number] => 10749466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749466
Dynamic relocation of execute in place applications Dec 30, 2003 Issued
Array ( [id] => 7261975 [patent_doc_number] => 20050144392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Fixed timeframe cache tag array arbitration mechanism for invalidations' [patent_app_type] => utility [patent_app_number] => 10/749435 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1000 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144392.pdf [firstpage_image] =>[orig_patent_app_number] => 10749435 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749435
Fixed timeframe cache tag array arbitration mechanism for invalidations Dec 29, 2003 Abandoned
Array ( [id] => 431344 [patent_doc_number] => 07269699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion' [patent_app_type] => utility [patent_app_number] => 10/733413 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 8925 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269699.pdf [firstpage_image] =>[orig_patent_app_number] => 10733413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733413
Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion Dec 11, 2003 Issued
Array ( [id] => 7100266 [patent_doc_number] => 20050132119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode current mirrors' [patent_app_type] => utility [patent_app_number] => 10/733474 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4762 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132119.pdf [firstpage_image] =>[orig_patent_app_number] => 10733474 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733474
Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode current mirrors Dec 11, 2003 Issued
Array ( [id] => 7222603 [patent_doc_number] => 20050055514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Data rearrangement method' [patent_app_type] => utility [patent_app_number] => 10/733302 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3574 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055514.pdf [firstpage_image] =>[orig_patent_app_number] => 10733302 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733302
Data rearrangement method Dec 11, 2003 Abandoned
Array ( [id] => 629809 [patent_doc_number] => 07136967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Multi-level cache having overlapping congruence groups of associativity sets in different cache levels' [patent_app_type] => utility [patent_app_number] => 10/731065 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8191 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136967.pdf [firstpage_image] =>[orig_patent_app_number] => 10731065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/731065
Multi-level cache having overlapping congruence groups of associativity sets in different cache levels Dec 8, 2003 Issued
Array ( [id] => 7148869 [patent_doc_number] => 20050120182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Method and apparatus for implementing cache coherence with adaptive write updates' [patent_app_type] => utility [patent_app_number] => 10/726787 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20050120182.pdf [firstpage_image] =>[orig_patent_app_number] => 10726787 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726787
Method and apparatus for implementing cache coherence with adaptive write updates Dec 1, 2003 Abandoned
Array ( [id] => 7456274 [patent_doc_number] => 20040165314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Portable storage device, method of controlling the same, control program for executing the method, and electronic information apparatus' [patent_app_type] => new [patent_app_number] => 10/726277 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10262 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20040165314.pdf [firstpage_image] =>[orig_patent_app_number] => 10726277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726277
Inhibiting access to a portable storage device Dec 1, 2003 Issued
Array ( [id] => 96852 [patent_doc_number] => 07734868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Universal RAID class driver' [patent_app_type] => utility [patent_app_number] => 10/726812 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3704 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734868.pdf [firstpage_image] =>[orig_patent_app_number] => 10726812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726812
Universal RAID class driver Dec 1, 2003 Issued
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