Search

Sharlene L Leurig

Examiner (ID: 918)

Most Active Art Unit
2879
Art Unit(s)
2879
Total Applications
146
Issued Applications
124
Pending Applications
2
Abandoned Applications
20

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13598477 [patent_doc_number] => 20180350787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => DISPLAY UNIT, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY UNIT [patent_app_type] => utility [patent_app_number] => 15/562219 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15562219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/562219
DISPLAY UNIT, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY UNIT Jan 26, 2017 Abandoned
Array ( [id] => 12223630 [patent_doc_number] => 20180061990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'ACTIVE LAYER, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS AND FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 15/534415 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7398 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15534415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/534415
ACTIVE LAYER, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS AND FABRICATION METHODS Dec 28, 2016 Abandoned
Array ( [id] => 12823570 [patent_doc_number] => 20180166362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR STACKING STRUCTURE AND METHOD FOR MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 15/378068 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378068 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378068
SEMICONDUCTOR STACKING STRUCTURE AND METHOD FOR MANUFACTURING THEREOF Dec 13, 2016 Abandoned
Array ( [id] => 12823741 [patent_doc_number] => 20180166419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/375498 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375498
SEMICONDUCTOR PACKAGE Dec 11, 2016 Abandoned
Array ( [id] => 11694675 [patent_doc_number] => 20170170392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'MAGNETORESISTANCE EFFECT ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/371987 [patent_app_country] => US [patent_app_date] => 2016-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10602 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15371987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/371987
Magnetoresistance effect element Dec 6, 2016 Issued
Array ( [id] => 11760428 [patent_doc_number] => 20170207296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/365115 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10541 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365115
High voltage junction field effect transistor (JFET) with spiral voltage divider Nov 29, 2016 Issued
Array ( [id] => 17048085 [patent_doc_number] => 11101275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Ferroelectric memory array surrounded by ferroelectric dummy capacitors [patent_app_type] => utility [patent_app_number] => 15/356749 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 8984 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 585 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356749
Ferroelectric memory array surrounded by ferroelectric dummy capacitors Nov 20, 2016 Issued
Array ( [id] => 11718337 [patent_doc_number] => 20170186837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DEEP TRENCH CAPACITOR WITH SCALLOP PROFILE' [patent_app_type] => utility [patent_app_number] => 15/356859 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356859 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356859
DEEP TRENCH CAPACITOR WITH SCALLOP PROFILE Nov 20, 2016 Abandoned
Array ( [id] => 15427753 [patent_doc_number] => 10546816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor substrate with electrically isolating dielectric partition [patent_app_type] => utility [patent_app_number] => 15/356527 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5342 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356527
Semiconductor substrate with electrically isolating dielectric partition Nov 17, 2016 Issued
Array ( [id] => 15427753 [patent_doc_number] => 10546816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor substrate with electrically isolating dielectric partition [patent_app_type] => utility [patent_app_number] => 15/356527 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5342 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356527
Semiconductor substrate with electrically isolating dielectric partition Nov 17, 2016 Issued
Array ( [id] => 11608016 [patent_doc_number] => 20170125319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'ELECTRONIC COMPONENT' [patent_app_type] => utility [patent_app_number] => 15/340915 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6523 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340915 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340915
ELECTRONIC COMPONENT Oct 31, 2016 Abandoned
Array ( [id] => 11652831 [patent_doc_number] => 20170148732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/333750 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 24201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333750 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333750
SEMICONDUCTOR DEVICE Oct 24, 2016 Abandoned
Array ( [id] => 12990010 [patent_doc_number] => 20170345739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => ADVANCED THROUGH SUBSTRATE VIA METALLIZATION IN THREE DIMENSIONAL SEMICONDUCTOR INTEGRATION [patent_app_type] => utility [patent_app_number] => 15/289187 [patent_app_country] => US [patent_app_date] => 2016-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289187 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289187
Advanced through substrate via metallization in three dimensional semiconductor integration Oct 8, 2016 Issued
Array ( [id] => 13378433 [patent_doc_number] => 20180240758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => SEMICONDUCTOR APPARATUS AND COMPOSITE SHEET [patent_app_type] => utility [patent_app_number] => 15/765184 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15765184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/765184
SEMICONDUCTOR APPARATUS AND COMPOSITE SHEET Oct 6, 2016 Abandoned
Array ( [id] => 17332514 [patent_doc_number] => 11222982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping [patent_app_type] => utility [patent_app_number] => 16/321356 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5565 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16321356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/321356
Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping Sep 28, 2016 Issued
Array ( [id] => 13470863 [patent_doc_number] => 20180286974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/765120 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15765120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/765120
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Sep 15, 2016 Abandoned
Array ( [id] => 15703551 [patent_doc_number] => 10607963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Chip package for two-phase cooling and assembly process thereof [patent_app_type] => utility [patent_app_number] => 15/266786 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7128 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/266786
Chip package for two-phase cooling and assembly process thereof Sep 14, 2016 Issued
Array ( [id] => 13405445 [patent_doc_number] => 20180254265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => MICRO- OR NANO-WIRE LED LIGHT SOURCE COMPRISING TEMPERATURE MEASUREMENT MEANS [patent_app_type] => utility [patent_app_number] => 15/759391 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15759391 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/759391
MICRO- OR NANO-WIRE LED LIGHT SOURCE COMPRISING TEMPERATURE MEASUREMENT MEANS Sep 12, 2016 Abandoned
Array ( [id] => 12223589 [patent_doc_number] => 20180061950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'TRANSISTOR DEVICE WITH THRESHOLD VOLTAGE ADJUSTED BY BODY EFFECT' [patent_app_type] => utility [patent_app_number] => 15/251829 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2295 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/251829
Transistor device with threshold voltage adjusted by body effect Aug 29, 2016 Issued
Array ( [id] => 15427819 [patent_doc_number] => 10546849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor structure for electrostatic discharge protection [patent_app_type] => utility [patent_app_number] => 15/247134 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2875 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247134
Semiconductor structure for electrostatic discharge protection Aug 24, 2016 Issued
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