Sharon Pregler

Array ( [id] => 5022823 [patent_doc_number] => 20070148789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'METHODS OF FORMING MAGNETIC RANDOM ACCESS MEMORY DEVICES HAVING TITANIUM-RICH LOWER ELECTRODES WITH OXIDE LAYER AND ORIENTED TUNNELING BARRIER' [patent_app_type] => utility [patent_app_number] => 11/673612 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5062 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148789.pdf [firstpage_image] =>[orig_patent_app_number] => 11673612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307335 [patent_doc_number] => 07531401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Method for improved fabrication of a semiconductor using a stress proximity technique process' [patent_app_type] => utility [patent_app_number] => 11/672572 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4390 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531401.pdf [firstpage_image] =>[orig_patent_app_number] => 11672572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5236649 [patent_doc_number] => 20070128806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'High performance CMOS transistors using PMD liner stress' [patent_app_type] => utility [patent_app_number] => 11/670192 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2247 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128806.pdf [firstpage_image] =>[orig_patent_app_number] => 11670192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4845962 [patent_doc_number] => 20080182370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/669401 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182370.pdf [firstpage_image] =>[orig_patent_app_number] => 11669401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5159984 [patent_doc_number] => 20070173028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method of forming dielectric film and capacitor manufacturing method using the same' [patent_app_type] => utility [patent_app_number] => 11/657022 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6853 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20070173028.pdf [firstpage_image] =>[orig_patent_app_number] => 11657022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5079695 [patent_doc_number] => 20070122919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method of producing an integrated circuit arrangement with field-shaping electrical conductors' [patent_app_type] => utility [patent_app_number] => 11/657256 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6626 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122919.pdf [firstpage_image] =>[orig_patent_app_number] => 11657256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 174188 [patent_doc_number] => 07659567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Semiconductor device featuring common capacitor electrode layer, and method for manufacturing such semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/656532 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 11276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/659/07659567.pdf [firstpage_image] =>[orig_patent_app_number] => 11656532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5095717 [patent_doc_number] => 20070117326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'MATERIAL ARCHITECTURE FOR THE FABRICATION OF LOW TEMPERATURE TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/625789 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9381 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117326.pdf [firstpage_image] =>[orig_patent_app_number] => 11625789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5008112 [patent_doc_number] => 20070278589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Semiconductor device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/654672 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7939 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20070278589.pdf [firstpage_image] =>[orig_patent_app_number] => 11654672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5219866 [patent_doc_number] => 20070161177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Semiconductor device having increased capacitance of capacitor for data storage and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/652072 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6978 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20070161177.pdf [firstpage_image] =>[orig_patent_app_number] => 11652072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 190835 [patent_doc_number] => 07642146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials' [patent_app_type] => utility [patent_app_number] => 11/620447 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 47 [patent_no_of_words] => 13016 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642146.pdf [firstpage_image] =>[orig_patent_app_number] => 11620447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 162296 [patent_doc_number] => 07670903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Method for fabricating a cylindrical capacitor using amorphous carbon-based layer' [patent_app_type] => utility [patent_app_number] => 11/646481 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 4572 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/670/07670903.pdf [firstpage_image] =>[orig_patent_app_number] => 11646481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 813680 [patent_doc_number] => 07413952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate' [patent_app_type] => utility [patent_app_number] => 11/646051 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3944 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413952.pdf [firstpage_image] =>[orig_patent_app_number] => 11646051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4876804 [patent_doc_number] => 20080150187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'MOLDED DIELECTRIC LAYER IN PRINT-PATTERNED ELECTRONIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/615229 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4486 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150187.pdf [firstpage_image] =>[orig_patent_app_number] => 11615229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5019566 [patent_doc_number] => 20070145532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'High voltage BICMOS device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/644202 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145532.pdf [firstpage_image] =>[orig_patent_app_number] => 11644202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5019565 [patent_doc_number] => 20070145531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/638111 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145531.pdf [firstpage_image] =>[orig_patent_app_number] => 11638111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4893479 [patent_doc_number] => 20080102577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method for Preparing a Trench Capacitor Structure' [patent_app_type] => utility [patent_app_number] => 11/564191 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1766 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20080102577.pdf [firstpage_image] =>[orig_patent_app_number] => 11564191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5022930 [patent_doc_number] => 20070148896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'MEMORY WITH MEMORY CELLS THAT INCLUDE A MIM TYPE CAPACITOR WITH A LOWER ELECTRODE MADE FOR REDUCED RESISTANCE AT AN INTERFACE WITH A METAL FILM' [patent_app_type] => utility [patent_app_number] => 11/563442 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10558 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148896.pdf [firstpage_image] =>[orig_patent_app_number] => 11563442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5120074 [patent_doc_number] => 20070141788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Method for embedding non-volatile memory with logic circuitry' [patent_app_type] => utility [patent_app_number] => 11/604237 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3529 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20070141788.pdf [firstpage_image] =>[orig_patent_app_number] => 11604237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4551075 [patent_doc_number] => 07820461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Semiconductor device with vertical electron injection and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/561685 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4221 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/820/07820461.pdf [firstpage_image] =>[orig_patent_app_number] => 11561685 [rel_patent_id] =>[rel_patent_doc_number] =>)