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Shawn M Buchanan

Examiner (ID: 13665)

Most Active Art Unit
2821
Art Unit(s)
2821
Total Applications
42
Issued Applications
25
Pending Applications
0
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4057717 [patent_doc_number] => 05875338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and apparatus for arbitrating resource requests utilizing independent tokens for arbiter cell selection' [patent_app_type] => 1 [patent_app_number] => 8/572400 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3922 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875338.pdf [firstpage_image] =>[orig_patent_app_number] => 572400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572400
Method and apparatus for arbitrating resource requests utilizing independent tokens for arbiter cell selection Dec 13, 1995 Issued
Array ( [id] => 4049060 [patent_doc_number] => 05943483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method and apparatus for controlling access to a bus in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/570153 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943483.pdf [firstpage_image] =>[orig_patent_app_number] => 570153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/570153
Method and apparatus for controlling access to a bus in a data processing system Dec 10, 1995 Issued
Array ( [id] => 4030931 [patent_doc_number] => 05881247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'System having a plurality of frame bytes capable of identifying addressed recipients and assert a busy signal onto the backplane bus to forthrightly abort the message transfer' [patent_app_type] => 1 [patent_app_number] => 8/537066 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 39668 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881247.pdf [firstpage_image] =>[orig_patent_app_number] => 537066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537066
System having a plurality of frame bytes capable of identifying addressed recipients and assert a busy signal onto the backplane bus to forthrightly abort the message transfer Nov 29, 1995 Issued
Array ( [id] => 4081375 [patent_doc_number] => 05867677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Switching adapter and method for a computer system' [patent_app_type] => 1 [patent_app_number] => 8/563614 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 9941 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867677.pdf [firstpage_image] =>[orig_patent_app_number] => 563614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563614
Switching adapter and method for a computer system Nov 27, 1995 Issued
Array ( [id] => 3970406 [patent_doc_number] => 05991846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Information processing apparatus with output device selection based on device characteristics and priorities' [patent_app_type] => 1 [patent_app_number] => 8/559814 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4369 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991846.pdf [firstpage_image] =>[orig_patent_app_number] => 559814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559814
Information processing apparatus with output device selection based on device characteristics and priorities Nov 16, 1995 Issued
Array ( [id] => 3806918 [patent_doc_number] => 05841996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Serial communication interface system having programmable microcontroller for use in a battery pack' [patent_app_type] => 1 [patent_app_number] => 8/542679 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 11342 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841996.pdf [firstpage_image] =>[orig_patent_app_number] => 542679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542679
Serial communication interface system having programmable microcontroller for use in a battery pack Oct 12, 1995 Issued
Array ( [id] => 3898461 [patent_doc_number] => 05805919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method and system for interleaving the distribution of data segments from different logical volumes on a single physical drive' [patent_app_type] => 1 [patent_app_number] => 8/538981 [patent_app_country] => US [patent_app_date] => 1995-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2708 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805919.pdf [firstpage_image] =>[orig_patent_app_number] => 538981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/538981
Method and system for interleaving the distribution of data segments from different logical volumes on a single physical drive Oct 4, 1995 Issued
Array ( [id] => 3806933 [patent_doc_number] => 05841997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Apparatus for effecting port switching of fibre channel loops' [patent_app_type] => 1 [patent_app_number] => 8/536686 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2484 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841997.pdf [firstpage_image] =>[orig_patent_app_number] => 536686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536686
Apparatus for effecting port switching of fibre channel loops Sep 28, 1995 Issued
Array ( [id] => 4017892 [patent_doc_number] => 05859988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Triple-port bus bridge' [patent_app_type] => 1 [patent_app_number] => 8/536275 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5274 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859988.pdf [firstpage_image] =>[orig_patent_app_number] => 536275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536275
Triple-port bus bridge Sep 28, 1995 Issued
Array ( [id] => 3897258 [patent_doc_number] => 05805842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Apparatus, system and method for supporting DMA transfers on a multiplexed bus' [patent_app_type] => 1 [patent_app_number] => 8/534187 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 2 [patent_no_of_words] => 3951 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805842.pdf [firstpage_image] =>[orig_patent_app_number] => 534187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534187
Apparatus, system and method for supporting DMA transfers on a multiplexed bus Sep 25, 1995 Issued
Array ( [id] => 4021562 [patent_doc_number] => 05987544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'System interface protocol with optional module cache' [patent_app_type] => 1 [patent_app_number] => 8/525114 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4864 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987544.pdf [firstpage_image] =>[orig_patent_app_number] => 525114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/525114
System interface protocol with optional module cache Sep 7, 1995 Issued
Array ( [id] => 3849349 [patent_doc_number] => 05761444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and apparatus for dynamically deferring transactions' [patent_app_type] => 1 [patent_app_number] => 8/523385 [patent_app_country] => US [patent_app_date] => 1995-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5744 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761444.pdf [firstpage_image] =>[orig_patent_app_number] => 523385 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/523385
Method and apparatus for dynamically deferring transactions Sep 4, 1995 Issued
08/518483 DIGITAL GATE COMPUTER BUS Aug 22, 1995 Abandoned
Array ( [id] => 4008535 [patent_doc_number] => 05892954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus for refreshing file locks to minimize conflicting accesses to data files' [patent_app_type] => 1 [patent_app_number] => 8/499591 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3474 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892954.pdf [firstpage_image] =>[orig_patent_app_number] => 499591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499591
Method and apparatus for refreshing file locks to minimize conflicting accesses to data files Jul 6, 1995 Issued
Array ( [id] => 3848841 [patent_doc_number] => 05740448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for exclusive access to shared data structures through index referenced buffers' [patent_app_type] => 1 [patent_app_number] => 8/499483 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4204 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740448.pdf [firstpage_image] =>[orig_patent_app_number] => 499483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499483
Method and apparatus for exclusive access to shared data structures through index referenced buffers Jul 6, 1995 Issued
Array ( [id] => 4076536 [patent_doc_number] => 05896540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and apparatus for controlling data transfer between a host and a peripheral in a pre-reading mode, post-reading mode and both-reading mode' [patent_app_type] => 1 [patent_app_number] => 8/496284 [patent_app_country] => US [patent_app_date] => 1995-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7242 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896540.pdf [firstpage_image] =>[orig_patent_app_number] => 496284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/496284
Method and apparatus for controlling data transfer between a host and a peripheral in a pre-reading mode, post-reading mode and both-reading mode Jun 27, 1995 Issued
Array ( [id] => 3830826 [patent_doc_number] => 05812861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Override signal for forcing a powerdown of a flash memory' [patent_app_type] => 1 [patent_app_number] => 8/493574 [patent_app_country] => US [patent_app_date] => 1995-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6908 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812861.pdf [firstpage_image] =>[orig_patent_app_number] => 493574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493574
Override signal for forcing a powerdown of a flash memory Jun 21, 1995 Issued
Array ( [id] => 3849315 [patent_doc_number] => 05761443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Computer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral bus' [patent_app_type] => 1 [patent_app_number] => 8/487063 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8070 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761443.pdf [firstpage_image] =>[orig_patent_app_number] => 487063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487063
Computer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral bus Jun 6, 1995 Issued
Array ( [id] => 3802408 [patent_doc_number] => 05737524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Add-in board with programmable configuration registers for use in PCI bus computers' [patent_app_type] => 1 [patent_app_number] => 8/446390 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5028 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737524.pdf [firstpage_image] =>[orig_patent_app_number] => 446390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/446390
Add-in board with programmable configuration registers for use in PCI bus computers May 21, 1995 Issued
08/421202 DUAL ARBITERS FOR ARBITRATING ACCESS TO A FIRST AND SECOND BUS IN A COMPUTER SYSTEM HAVING BUS MASTERS ON EACH BUS Apr 12, 1995 Abandoned
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