Shawn Riley

Array ( [id] => 3055459 [patent_doc_number] => 05306971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Binary controlled digital tapped delay line' [patent_app_type] => 1 [patent_app_number] => 7/917386 [patent_app_country] => US [patent_app_date] => 1992-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4575 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/306/05306971.pdf [firstpage_image] =>[orig_patent_app_number] => 917386 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3456817 [patent_doc_number] => 05420904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Signal averager' [patent_app_type] => 1 [patent_app_number] => 7/918621 [patent_app_country] => US [patent_app_date] => 1992-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3762 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420904.pdf [firstpage_image] =>[orig_patent_app_number] => 918621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3134744 [patent_doc_number] => 05436819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Apparatus for and method of compensating for an output voltage error in an inverter output' [patent_app_type] => 1 [patent_app_number] => 7/915346 [patent_app_country] => US [patent_app_date] => 1992-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 5283 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436819.pdf [firstpage_image] =>[orig_patent_app_number] => 915346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3012064 [patent_doc_number] => 05331213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Pulse transmission circuit with undershoot eliminating circuitry' [patent_app_type] => 1 [patent_app_number] => 7/910507 [patent_app_country] => US [patent_app_date] => 1992-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 3914 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/331/05331213.pdf [firstpage_image] =>[orig_patent_app_number] => 910507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3017825 [patent_doc_number] => 05309037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Power-on reset circuit with arbitrary output prevention' [patent_app_type] => 1 [patent_app_number] => 7/910194 [patent_app_country] => US [patent_app_date] => 1992-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2589 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/309/05309037.pdf [firstpage_image] =>[orig_patent_app_number] => 910194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3097776 [patent_doc_number] => 05313118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'High-speed, low-noise, CMOS output driver' [patent_app_type] => 1 [patent_app_number] => 7/909549 [patent_app_country] => US [patent_app_date] => 1992-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2311 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313118.pdf [firstpage_image] =>[orig_patent_app_number] => 909549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061898 [patent_doc_number] => 05350952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-27 [patent_title] => 'Sample and hold circuit with push-pull output charging current' [patent_app_type] => 1 [patent_app_number] => 7/909286 [patent_app_country] => US [patent_app_date] => 1992-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3229 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/350/05350952.pdf [firstpage_image] =>[orig_patent_app_number] => 909286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3431927 [patent_doc_number] => 05390223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Divider circuit structure' [patent_app_type] => 1 [patent_app_number] => 7/907189 [patent_app_country] => US [patent_app_date] => 1992-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1863 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390223.pdf [firstpage_image] =>[orig_patent_app_number] => 907189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2995423 [patent_doc_number] => 05347174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Circuit arrangement for converting a voltage drop tapped from a test object from a predetermined input voltage range to a desired output voltage range' [patent_app_type] => 1 [patent_app_number] => 7/907269 [patent_app_country] => US [patent_app_date] => 1992-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1988 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347174.pdf [firstpage_image] =>[orig_patent_app_number] => 907269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3090879 [patent_doc_number] => 05285122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Variable delay device' [patent_app_type] => 1 [patent_app_number] => 7/904689 [patent_app_country] => US [patent_app_date] => 1992-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3064 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285122.pdf [firstpage_image] =>[orig_patent_app_number] => 904689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467005 [patent_doc_number] => 05391981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Current source adapted to allow for rapid output voltage fluctuations' [patent_app_type] => 1 [patent_app_number] => 7/897819 [patent_app_country] => US [patent_app_date] => 1992-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2021 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391981.pdf [firstpage_image] =>[orig_patent_app_number] => 897819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3025461 [patent_doc_number] => 05289059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Switched capacitor decimator' [patent_app_type] => 1 [patent_app_number] => 7/893752 [patent_app_country] => US [patent_app_date] => 1992-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3520 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289059.pdf [firstpage_image] =>[orig_patent_app_number] => 893752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3101943 [patent_doc_number] => 05298866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Clock distribution circuit with active de-skewing' [patent_app_type] => 1 [patent_app_number] => 7/893450 [patent_app_country] => US [patent_app_date] => 1992-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5311 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298866.pdf [firstpage_image] =>[orig_patent_app_number] => 893450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3080519 [patent_doc_number] => 05296766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'CMOS circuit with crowbar limiting function' [patent_app_type] => 1 [patent_app_number] => 7/894368 [patent_app_country] => US [patent_app_date] => 1992-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296766.pdf [firstpage_image] =>[orig_patent_app_number] => 894368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3077497 [patent_doc_number] => 05365118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Circuit for driving two power mosfets in a half-bridge configuration' [patent_app_type] => 1 [patent_app_number] => 7/893523 [patent_app_country] => US [patent_app_date] => 1992-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5518 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365118.pdf [firstpage_image] =>[orig_patent_app_number] => 893523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3000108 [patent_doc_number] => 05362992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Electronic control of peak detector response time' [patent_app_type] => 1 [patent_app_number] => 7/891245 [patent_app_country] => US [patent_app_date] => 1992-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2352 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362992.pdf [firstpage_image] =>[orig_patent_app_number] => 891245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3104665 [patent_doc_number] => 05315184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Self arbitrating auto resettable flag circuit' [patent_app_type] => 1 [patent_app_number] => 7/878201 [patent_app_country] => US [patent_app_date] => 1992-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315184.pdf [firstpage_image] =>[orig_patent_app_number] => 878201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3088275 [patent_doc_number] => 05297179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Doubling circuit' [patent_app_type] => 1 [patent_app_number] => 7/874631 [patent_app_country] => US [patent_app_date] => 1992-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1931 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297179.pdf [firstpage_image] =>[orig_patent_app_number] => 874631 [rel_patent_id] =>[rel_patent_doc_number] =>)