Search

Shawn X. Gu

Examiner (ID: 12057, Phone: (571)272-0703 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2189
Total Applications
1301
Issued Applications
1187
Pending Applications
49
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8319666 [patent_doc_number] => 08234459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Switch module based non-volatile memory in a server' [patent_app_type] => utility [patent_app_number] => 12/403712 [patent_app_country] => US [patent_app_date] => 2009-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2209 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12403712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/403712
Switch module based non-volatile memory in a server Mar 12, 2009 Issued
Array ( [id] => 5369879 [patent_doc_number] => 20090307438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Automated Paging Device Management in a Shared Memory Partition Data Processing System' [patent_app_type] => utility [patent_app_number] => 12/403426 [patent_app_country] => US [patent_app_date] => 2009-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307438.pdf [firstpage_image] =>[orig_patent_app_number] => 12403426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/403426
Automated paging device management in a shared memory partition data processing system Mar 12, 2009 Issued
Array ( [id] => 7746316 [patent_doc_number] => 08108648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Various methods and apparatus for address tiling' [patent_app_type] => utility [patent_app_number] => 12/402704 [patent_app_country] => US [patent_app_date] => 2009-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12191 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108648.pdf [firstpage_image] =>[orig_patent_app_number] => 12402704 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402704
Various methods and apparatus for address tiling Mar 11, 2009 Issued
Array ( [id] => 7993035 [patent_doc_number] => 08078825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Composite hash and list partitioning of database tables' [patent_app_type] => utility [patent_app_number] => 12/402024 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8713 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078825.pdf [firstpage_image] =>[orig_patent_app_number] => 12402024 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402024
Composite hash and list partitioning of database tables Mar 10, 2009 Issued
Array ( [id] => 6639435 [patent_doc_number] => 20100005229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE' [patent_app_type] => utility [patent_app_number] => 12/400149 [patent_app_country] => US [patent_app_date] => 2009-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005229.pdf [firstpage_image] =>[orig_patent_app_number] => 12400149 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/400149
Flash memory apparatus and method for securing a flash memory from data damage Mar 8, 2009 Issued
Array ( [id] => 7718446 [patent_doc_number] => 08095765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Memory block management' [patent_app_type] => utility [patent_app_number] => 12/397396 [patent_app_country] => US [patent_app_date] => 2009-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 14782 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095765.pdf [firstpage_image] =>[orig_patent_app_number] => 12397396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/397396
Memory block management Mar 3, 2009 Issued
Array ( [id] => 6563982 [patent_doc_number] => 20100223427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'SYSTEM FOR HANDLING INPUT/OUTPUT REQUESTS BETWEEN STORAGE ARRAYS WITH DIFFERENT PERFORMANCE CAPABILITIES' [patent_app_type] => utility [patent_app_number] => 12/395786 [patent_app_country] => US [patent_app_date] => 2009-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223427.pdf [firstpage_image] =>[orig_patent_app_number] => 12395786 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/395786
System for handling input/output requests between storage arrays with different performance capabilities Mar 1, 2009 Issued
Array ( [id] => 6564257 [patent_doc_number] => 20100223447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Translate and Verify Instruction for a Processor' [patent_app_type] => utility [patent_app_number] => 12/394293 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223447.pdf [firstpage_image] =>[orig_patent_app_number] => 12394293 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/394293
Translate and verify instruction for a processor Feb 26, 2009 Issued
Array ( [id] => 7779810 [patent_doc_number] => 08122199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Multi port memory device with shared memory area using latch type memory cells and driving method' [patent_app_type] => utility [patent_app_number] => 12/392432 [patent_app_country] => US [patent_app_date] => 2009-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6177 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122199.pdf [firstpage_image] =>[orig_patent_app_number] => 12392432 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/392432
Multi port memory device with shared memory area using latch type memory cells and driving method Feb 24, 2009 Issued
Array ( [id] => 5516636 [patent_doc_number] => 20090216943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Data storage device and data management method in data storage device' [patent_app_type] => utility [patent_app_number] => 12/380116 [patent_app_country] => US [patent_app_date] => 2009-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20090216943.pdf [firstpage_image] =>[orig_patent_app_number] => 12380116 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/380116
Data storage device and data management method in data storage device Feb 22, 2009 Issued
Array ( [id] => 6387469 [patent_doc_number] => 20100082884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'MEMORY CELL OPERATION' [patent_app_type] => utility [patent_app_number] => 12/388366 [patent_app_country] => US [patent_app_date] => 2009-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11512 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082884.pdf [firstpage_image] =>[orig_patent_app_number] => 12388366 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/388366
Memory cell operation Feb 17, 2009 Issued
Array ( [id] => 6523261 [patent_doc_number] => 20100211745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'MEMORY PREFETCH SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/371389 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5644 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20100211745.pdf [firstpage_image] =>[orig_patent_app_number] => 12371389 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371389
Memory prefetch systems and methods Feb 12, 2009 Issued
Array ( [id] => 7798369 [patent_doc_number] => 08127087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Memory controller for improved read port selection in a memory mirrored system' [patent_app_type] => utility [patent_app_number] => 12/369806 [patent_app_country] => US [patent_app_date] => 2009-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3370 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127087.pdf [firstpage_image] =>[orig_patent_app_number] => 12369806 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/369806
Memory controller for improved read port selection in a memory mirrored system Feb 11, 2009 Issued
Array ( [id] => 6553990 [patent_doc_number] => 20100205368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'METHOD AND SYSTEM FOR CACHING DATA IN A STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/369486 [patent_app_country] => US [patent_app_date] => 2009-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205368.pdf [firstpage_image] =>[orig_patent_app_number] => 12369486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/369486
Method and system for caching data in a storgae system Feb 10, 2009 Issued
Array ( [id] => 6008837 [patent_doc_number] => 20110060868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES' [patent_app_type] => utility [patent_app_number] => 12/867882 [patent_app_country] => US [patent_app_date] => 2009-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8006 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20110060868.pdf [firstpage_image] =>[orig_patent_app_number] => 12867882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/867882
MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES Feb 9, 2009 Abandoned
Array ( [id] => 6553569 [patent_doc_number] => 20100205344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'UNIFIED CACHE STRUCTURE THAT FACILITATES ACCESSING TRANSLATION TABLE ENTRIES' [patent_app_type] => utility [patent_app_number] => 12/367828 [patent_app_country] => US [patent_app_date] => 2009-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205344.pdf [firstpage_image] =>[orig_patent_app_number] => 12367828 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/367828
Unified cache structure that facilitates accessing translation table entries Feb 8, 2009 Issued
Array ( [id] => 6413544 [patent_doc_number] => 20100306498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'STORAGE SYSTEM AND STORAGE CONTROL METHOD THAT COMPRESS AND STORE DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/310107 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14758 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306498.pdf [firstpage_image] =>[orig_patent_app_number] => 12310107 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/310107
Storage system and storage control method that compress and store data elements Jan 29, 2009 Issued
Array ( [id] => 9242222 [patent_doc_number] => 08607028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Enhanced addressability for serial non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/143072 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4952 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13143072 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/143072
Enhanced addressability for serial non-volatile memory Dec 29, 2008 Issued
Array ( [id] => 8176493 [patent_doc_number] => 20120110246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/143078 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110246.pdf [firstpage_image] =>[orig_patent_app_number] => 13143078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/143078
Execute-in-place mode configuration for serial non-volatile memory Dec 29, 2008 Issued
Array ( [id] => 7714089 [patent_doc_number] => 20120005411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/143075 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005411.pdf [firstpage_image] =>[orig_patent_app_number] => 13143075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/143075
Non-volatile configuration for serial non-volatile memory Dec 29, 2008 Issued
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