
Shawntina T. Fuqua
Examiner (ID: 5212, Phone: (571)272-4779 , Office: P/3742 )
| Most Active Art Unit | 3742 |
| Art Unit(s) | 3742, 3761 |
| Total Applications | 2140 |
| Issued Applications | 1705 |
| Pending Applications | 63 |
| Abandoned Applications | 375 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 522455
[patent_doc_number] => 07190055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Lead frame and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/396608
[patent_app_country] => US
[patent_app_date] => 2006-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5892
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11396608
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/396608 | Lead frame and semiconductor device | Apr 3, 2006 | Issued |
Array
(
[id] => 526073
[patent_doc_number] => 07187051
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-06
[patent_title] => 'Solid image-pickup device and method for manufacturing the solid image pickup device'
[patent_app_type] => utility
[patent_app_number] => 11/303297
[patent_app_country] => US
[patent_app_date] => 2005-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4032
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/187/07187051.pdf
[firstpage_image] =>[orig_patent_app_number] => 11303297
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/303297 | Solid image-pickup device and method for manufacturing the solid image pickup device | Dec 15, 2005 | Issued |
Array
(
[id] => 457625
[patent_doc_number] => 07245004
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/262967
[patent_app_country] => US
[patent_app_date] => 2005-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 8164
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/245/07245004.pdf
[firstpage_image] =>[orig_patent_app_number] => 11262967
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/262967 | Semiconductor device | Oct 31, 2005 | Issued |
Array
(
[id] => 522167
[patent_doc_number] => 07190030
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-13
[patent_title] => 'Electrostatic discharge protection structure'
[patent_app_type] => utility
[patent_app_number] => 11/221489
[patent_app_country] => US
[patent_app_date] => 2005-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2508
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190030.pdf
[firstpage_image] =>[orig_patent_app_number] => 11221489
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/221489 | Electrostatic discharge protection structure | Sep 6, 2005 | Issued |
Array
(
[id] => 408761
[patent_doc_number] => 07285827
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-23
[patent_title] => 'Back-to-back NPN/PNP protection diodes'
[patent_app_type] => utility
[patent_app_number] => 11/194449
[patent_app_country] => US
[patent_app_date] => 2005-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3909
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/285/07285827.pdf
[firstpage_image] =>[orig_patent_app_number] => 11194449
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/194449 | Back-to-back NPN/PNP protection diodes | Aug 1, 2005 | Issued |
Array
(
[id] => 7206219
[patent_doc_number] => 20050258488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Serially connected thin film transistors and fabrication methods thereof'
[patent_app_type] => utility
[patent_app_number] => 11/189479
[patent_app_country] => US
[patent_app_date] => 2005-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5569
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0258/20050258488.pdf
[firstpage_image] =>[orig_patent_app_number] => 11189479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/189479 | Serially connected thin film transistors and fabrication methods thereof | Jul 25, 2005 | Abandoned |
Array
(
[id] => 457667
[patent_doc_number] => 07245013
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Substrate based IC-package'
[patent_app_type] => utility
[patent_app_number] => 11/190068
[patent_app_country] => US
[patent_app_date] => 2005-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1842
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/245/07245013.pdf
[firstpage_image] =>[orig_patent_app_number] => 11190068
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/190068 | Substrate based IC-package | Jul 25, 2005 | Issued |
Array
(
[id] => 5848643
[patent_doc_number] => 20060231895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Guardwall structures for ESD protection'
[patent_app_type] => utility
[patent_app_number] => 11/155062
[patent_app_country] => US
[patent_app_date] => 2005-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3713
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20060231895.pdf
[firstpage_image] =>[orig_patent_app_number] => 11155062
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/155062 | Guardwall structures for ESD protection | Jun 16, 2005 | Issued |
Array
(
[id] => 436192
[patent_doc_number] => 07262450
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-28
[patent_title] => 'MFS type field effect transistor, its manufacturing method, ferroelectric memory and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/108933
[patent_app_country] => US
[patent_app_date] => 2005-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 80
[patent_no_of_words] => 12281
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/262/07262450.pdf
[firstpage_image] =>[orig_patent_app_number] => 11108933
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/108933 | MFS type field effect transistor, its manufacturing method, ferroelectric memory and semiconductor device | Apr 18, 2005 | Issued |
Array
(
[id] => 465237
[patent_doc_number] => 07238990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Interlayer dielectric under stress for an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/100168
[patent_app_country] => US
[patent_app_date] => 2005-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 2400
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/238/07238990.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100168
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100168 | Interlayer dielectric under stress for an integrated circuit | Apr 5, 2005 | Issued |
Array
(
[id] => 495679
[patent_doc_number] => 07211837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Insulated gate semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/076889
[patent_app_country] => US
[patent_app_date] => 2005-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 7095
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/211/07211837.pdf
[firstpage_image] =>[orig_patent_app_number] => 11076889
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/076889 | Insulated gate semiconductor device | Mar 10, 2005 | Issued |
Array
(
[id] => 5718533
[patent_doc_number] => 20060071306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'Active device bases, leadframes utilizing the same, and leadframe fabrication methods'
[patent_app_type] => utility
[patent_app_number] => 11/023749
[patent_app_country] => US
[patent_app_date] => 2004-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2453
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20060071306.pdf
[firstpage_image] =>[orig_patent_app_number] => 11023749
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/023749 | Active device bases, leadframes utilizing the same, and leadframe fabrication methods | Dec 27, 2004 | Abandoned |
Array
(
[id] => 5908880
[patent_doc_number] => 20060124975
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Dual work function gate in CMOS device'
[patent_app_type] => utility
[patent_app_number] => 11/008435
[patent_app_country] => US
[patent_app_date] => 2004-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1518
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20060124975.pdf
[firstpage_image] =>[orig_patent_app_number] => 11008435
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/008435 | Dual work function gate in CMOS device | Dec 8, 2004 | Abandoned |
Array
(
[id] => 7236615
[patent_doc_number] => 20050139987
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 10/986318
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 6574
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0139/20050139987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986318
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986318 | Semiconductor integrated circuit device | Nov 11, 2004 | Abandoned |
Array
(
[id] => 645209
[patent_doc_number] => 07118962
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'Nonvolatile memory device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/982005
[patent_app_country] => US
[patent_app_date] => 2004-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3187
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/118/07118962.pdf
[firstpage_image] =>[orig_patent_app_number] => 10982005
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/982005 | Nonvolatile memory device and method for manufacturing the same | Nov 3, 2004 | Issued |
Array
(
[id] => 387004
[patent_doc_number] => 07304373
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-04
[patent_title] => 'Power distribution within a folded flex package method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/977908
[patent_app_country] => US
[patent_app_date] => 2004-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 1953
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/304/07304373.pdf
[firstpage_image] =>[orig_patent_app_number] => 10977908
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/977908 | Power distribution within a folded flex package method and apparatus | Oct 27, 2004 | Issued |
Array
(
[id] => 6915592
[patent_doc_number] => 20050093153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'BGA package with component protection on bottom'
[patent_app_type] => utility
[patent_app_number] => 10/973409
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2198
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20050093153.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973409
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973409 | BGA package with component protection on bottom | Oct 26, 2004 | Abandoned |
Array
(
[id] => 484545
[patent_doc_number] => 07221058
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-22
[patent_title] => 'Substrate for mounting semiconductor chip, mounting structure of semiconductor chip, and mounting method of semiconductor chip'
[patent_app_type] => utility
[patent_app_number] => 10/950400
[patent_app_country] => US
[patent_app_date] => 2004-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 48
[patent_no_of_words] => 15644
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/221/07221058.pdf
[firstpage_image] =>[orig_patent_app_number] => 10950400
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/950400 | Substrate for mounting semiconductor chip, mounting structure of semiconductor chip, and mounting method of semiconductor chip | Sep 27, 2004 | Issued |
Array
(
[id] => 7242124
[patent_doc_number] => 20050073050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'BGA package and printed circuit board for supporting the package'
[patent_app_type] => utility
[patent_app_number] => 10/950436
[patent_app_country] => US
[patent_app_date] => 2004-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2239
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073050.pdf
[firstpage_image] =>[orig_patent_app_number] => 10950436
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/950436 | BGA package and printed circuit board for supporting the package | Sep 27, 2004 | Abandoned |
Array
(
[id] => 7114388
[patent_doc_number] => 20050067688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps'
[patent_app_type] => utility
[patent_app_number] => 10/949693
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 35427
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20050067688.pdf
[firstpage_image] =>[orig_patent_app_number] => 10949693
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/949693 | Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps | Sep 23, 2004 | Issued |