Search

Sheikh Maruf

Examiner (ID: 9095, Phone: (571)270-1903 , Office: P/2828 )

Most Active Art Unit
2828
Art Unit(s)
2828, 2823, 2897
Total Applications
855
Issued Applications
721
Pending Applications
70
Abandoned Applications
82

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16356660 [patent_doc_number] => 10797178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Multi-gate FinFET including negative capacitor, method of manufacturing the same, and electronic device [patent_app_type] => utility [patent_app_number] => 16/054809 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 7062 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054809
Multi-gate FinFET including negative capacitor, method of manufacturing the same, and electronic device Aug 2, 2018 Issued
Array ( [id] => 13598857 [patent_doc_number] => 20180350977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/052981 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 464 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052981
Power semiconductor device Aug 1, 2018 Issued
Array ( [id] => 14109995 [patent_doc_number] => 20190096673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => APPARATUS FOR FORMING A LAYER ON A SUBSTRATE AND METHOD OF FORMING AN AMORPHOUS SILICON LAYER ON A SUBSTRATE USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/052063 [patent_app_country] => US [patent_app_date] => 2018-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052063
APPARATUS FOR FORMING A LAYER ON A SUBSTRATE AND METHOD OF FORMING AN AMORPHOUS SILICON LAYER ON A SUBSTRATE USING THE SAME Jul 31, 2018 Abandoned
Array ( [id] => 16067527 [patent_doc_number] => 10692725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Directed self-assembly process with size-restricted guiding patterns [patent_app_type] => utility [patent_app_number] => 16/041892 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 73 [patent_no_of_words] => 7188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041892
Directed self-assembly process with size-restricted guiding patterns Jul 22, 2018 Issued
Array ( [id] => 13559471 [patent_doc_number] => 20180331283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => Array Of Cross Point Memory Cells [patent_app_type] => utility [patent_app_number] => 16/041374 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041374
Array of cross point memory cells Jul 19, 2018 Issued
Array ( [id] => 13496167 [patent_doc_number] => 20180299626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => METHOD OF FORMING PHOTONICS STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/015778 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015778 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015778
Method of forming photonics structures Jun 21, 2018 Issued
Array ( [id] => 16981416 [patent_doc_number] => 20210225653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => LASER ANNEALING METHOD, LASER ANNEALING APPARATUS AND METHOD FOR PRODUCING ACTIVE MATRIX SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/734070 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15734070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/734070
LASER ANNEALING METHOD, LASER ANNEALING APPARATUS AND METHOD FOR PRODUCING ACTIVE MATRIX SUBSTRATE Jun 5, 2018 Abandoned
Array ( [id] => 14800961 [patent_doc_number] => 10403490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 15/977418 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 10264 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15977418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/977418
Wafer processing method May 10, 2018 Issued
Array ( [id] => 13405665 [patent_doc_number] => 20180254375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => METHOD FOR MANUFACTURING CRYSTALLINE SILICON-BASED SOLAR CELL AND METHOD FOR MANUFACTURING CRYSTALLINE SILICON-BASED SOLAR CELL MODULE [patent_app_type] => utility [patent_app_number] => 15/971744 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971744 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971744
Method for manufacturing crystalline silicon-based solar cell and method for manufacturing crystalline silicon-based solar cell module May 3, 2018 Issued
Array ( [id] => 17574270 [patent_doc_number] => 11322545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Vertical JFET device for memristor array interface [patent_app_type] => utility [patent_app_number] => 17/041382 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5753 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17041382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/041382
Vertical JFET device for memristor array interface Apr 26, 2018 Issued
Array ( [id] => 17803477 [patent_doc_number] => 11417790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Avalanche photodetectors and image sensors including the same [patent_app_type] => utility [patent_app_number] => 15/942659 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 9073 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942659
Avalanche photodetectors and image sensors including the same Apr 1, 2018 Issued
Array ( [id] => 13334805 [patent_doc_number] => 20180218940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS [patent_app_type] => utility [patent_app_number] => 15/926870 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926870 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926870
Conformal low temperature hermetic dielectric diffusion barriers Mar 19, 2018 Issued
Array ( [id] => 16339417 [patent_doc_number] => 10790387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => High voltage LDMOS transistor and methods for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/912191 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912191
High voltage LDMOS transistor and methods for manufacturing the same Mar 4, 2018 Issued
Array ( [id] => 12872734 [patent_doc_number] => 20180182753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => FIN-SHAPED FIELD EFFECT TRANSISTOR AND CAPACITOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/902934 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15902934 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/902934
Fin-shaped field effect transistor and capacitor structures Feb 21, 2018 Issued
Array ( [id] => 15985271 [patent_doc_number] => 10672975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Magnetic tunnel junction with reduced damage [patent_app_type] => utility [patent_app_number] => 15/894656 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 6645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894656 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/894656
Magnetic tunnel junction with reduced damage Feb 11, 2018 Issued
Array ( [id] => 12800698 [patent_doc_number] => 20180158735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => PARTITIONED WAFER AND SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 15/890041 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890041
Partitioned wafer and semiconductor die Feb 5, 2018 Issued
Array ( [id] => 15388681 [patent_doc_number] => 10535538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => System and method for heat treatment of substrates [patent_app_type] => utility [patent_app_number] => 15/880935 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880935
System and method for heat treatment of substrates Jan 25, 2018 Issued
Array ( [id] => 16180758 [patent_doc_number] => 20200227727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => High Power Lithium Ion Battery and the Method to Form [patent_app_type] => utility [patent_app_number] => 16/517598 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -42 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517598
High Power Lithium Ion Battery and the Method to Form Jan 18, 2018 Abandoned
Array ( [id] => 16316320 [patent_doc_number] => 20200295058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => METHOD OF PREPARING IGZO THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/749492 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/749492
Method of preparing IGZO thin film transistor Jan 3, 2018 Issued
Array ( [id] => 17745849 [patent_doc_number] => 11393934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => FinFET based capacitors and resistors and related apparatuses, systems, and methods [patent_app_type] => utility [patent_app_number] => 16/650321 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8894 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/650321
FinFET based capacitors and resistors and related apparatuses, systems, and methods Dec 26, 2017 Issued
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