Sheila V. Clark

Array ( [id] => 7071129 [patent_doc_number] => 20050246514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Information processing apparatus and method of system control of the apparatus' [patent_app_type] => utility [patent_app_number] => 11/088530 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4119 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20050246514.pdf [firstpage_image] =>[orig_patent_app_number] => 11088530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7474117 [patent_doc_number] => 20040168020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Memory device interface' [patent_app_type] => new [patent_app_number] => 10/789290 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3937 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168020.pdf [firstpage_image] =>[orig_patent_app_number] => 10789290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7678307 [patent_doc_number] => 20030196029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Method of writing, erasing, and controlling memory for memory device' [patent_app_type] => new [patent_app_number] => 10/446810 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 16950 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196029.pdf [firstpage_image] =>[orig_patent_app_number] => 10446810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6810469 [patent_doc_number] => 20030200408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method and apparatus for reducing latency in a memory system by interleaving SRAM and DRAM accesses' [patent_app_type] => new [patent_app_number] => 10/444600 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9918 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200408.pdf [firstpage_image] =>[orig_patent_app_number] => 10444600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1233710 [patent_doc_number] => 06697803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Generating searchable data entries and applications therefore' [patent_app_type] => B2 [patent_app_number] => 10/272949 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9672 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697803.pdf [firstpage_image] =>[orig_patent_app_number] => 10272949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6775510 [patent_doc_number] => 20030018848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Memory device interface' [patent_app_type] => new [patent_app_number] => 10/238117 [patent_app_country] => US [patent_app_date] => 2002-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3869 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018848.pdf [firstpage_image] =>[orig_patent_app_number] => 10238117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6051396 [patent_doc_number] => 20020169920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Information processing system and semiconductor intergrated circuit' [patent_app_type] => new [patent_app_number] => 10/186891 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7237 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20020169920.pdf [firstpage_image] =>[orig_patent_app_number] => 10186891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 987607 [patent_doc_number] => 06925485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-02 [patent_title] => 'Proxy cache preloader' [patent_app_type] => utility [patent_app_number] => 10/155694 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5677 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925485.pdf [firstpage_image] =>[orig_patent_app_number] => 10155694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1323997 [patent_doc_number] => 06611897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Method and apparatus for implementing redundancy on data stored in a disk array subsystem based on use frequency or importance of the data' [patent_app_type] => B2 [patent_app_number] => 10/123404 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4304 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611897.pdf [firstpage_image] =>[orig_patent_app_number] => 10123404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6771118 [patent_doc_number] => 20030217058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Lock-free file system' [patent_app_type] => new [patent_app_number] => 10/106486 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11453 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20030217058.pdf [firstpage_image] =>[orig_patent_app_number] => 10106486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431165 [patent_doc_number] => 06523090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Shared instruction cache for multiple processors' [patent_app_type] => B2 [patent_app_number] => 10/100263 [patent_app_country] => US [patent_app_date] => 2002-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4300 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523090.pdf [firstpage_image] =>[orig_patent_app_number] => 10100263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1385839 [patent_doc_number] => 06571315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method and apparatus for cache memory management' [patent_app_type] => B2 [patent_app_number] => 09/989266 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2824 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571315.pdf [firstpage_image] =>[orig_patent_app_number] => 09989266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1033696 [patent_doc_number] => 06880045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Multi-processor computer system with transactional memory' [patent_app_type] => utility [patent_app_number] => 09/976495 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2356 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/880/06880045.pdf [firstpage_image] =>[orig_patent_app_number] => 09976495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7622382 [patent_doc_number] => 06687784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Controller for controlling nonvolatile memory unit' [patent_app_type] => B2 [patent_app_number] => 09/954015 [patent_app_country] => US [patent_app_date] => 2001-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8175 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687784.pdf [firstpage_image] =>[orig_patent_app_number] => 09954015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6606632 [patent_doc_number] => 20020042865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Priority encoder circuit and method' [patent_app_type] => new [patent_app_number] => 09/954074 [patent_app_country] => US [patent_app_date] => 2001-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20020042865.pdf [firstpage_image] =>[orig_patent_app_number] => 09954074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6722368 [patent_doc_number] => 20030056058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Logical volume data migration' [patent_app_type] => new [patent_app_number] => 09/954104 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3816 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056058.pdf [firstpage_image] =>[orig_patent_app_number] => 09954104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1218280 [patent_doc_number] => 06711690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Secure write blocking circuit and method for preventing unauthorized write access to nonvolatile memory' [patent_app_type] => B2 [patent_app_number] => 09/953775 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3288 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711690.pdf [firstpage_image] =>[orig_patent_app_number] => 09953775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6722384 [patent_doc_number] => 20030056074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Memory system having cells of varying sizes' [patent_app_type] => new [patent_app_number] => 09/953356 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2054 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056074.pdf [firstpage_image] =>[orig_patent_app_number] => 09953356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6554684 [patent_doc_number] => 20020194452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Modulo addressing based on absolute offset' [patent_app_type] => new [patent_app_number] => 09/870445 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194452.pdf [firstpage_image] =>[orig_patent_app_number] => 09870445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1289217 [patent_doc_number] => 06647483 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Address translation circuit for processors utilizing a single code image' [patent_app_type] => B1 [patent_app_number] => 09/872883 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2661 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647483.pdf [firstpage_image] =>[orig_patent_app_number] => 09872883 [rel_patent_id] =>[rel_patent_doc_number] =>)