Sheila V. Clark

Array ( [id] => 3661316 [patent_doc_number] => 05640594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method and system for assigning peripheral device addresses' [patent_app_type] => 1 [patent_app_number] => 8/679650 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3067 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640594.pdf [firstpage_image] =>[orig_patent_app_number] => 679650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180373 [patent_doc_number] => 06751160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Memory control with burst-access capability' [patent_app_type] => B1 [patent_app_number] => 08/678699 [patent_app_country] => US [patent_app_date] => 1996-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5112 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751160.pdf [firstpage_image] =>[orig_patent_app_number] => 08678699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633033 [patent_doc_number] => 05608536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'System printer' [patent_app_type] => 1 [patent_app_number] => 8/674219 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3916 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608536.pdf [firstpage_image] =>[orig_patent_app_number] => 674219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3784390 [patent_doc_number] => 05734849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Dual bus memory transactions using address bus for data transfer' [patent_app_type] => 1 [patent_app_number] => 8/673055 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3451 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734849.pdf [firstpage_image] =>[orig_patent_app_number] => 673055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3872323 [patent_doc_number] => 05768557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Low cost writethrough cache coherency apparatus and method for computer systems without a cache suppporting bus' [patent_app_type] => 1 [patent_app_number] => 8/664138 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8987 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768557.pdf [firstpage_image] =>[orig_patent_app_number] => 664138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758762 [patent_doc_number] => 05787468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Computer system with a cache coherent non-uniform memory access architecture using a fast tag cache to accelerate memory references' [patent_app_type] => 1 [patent_app_number] => 8/665065 [patent_app_country] => US [patent_app_date] => 1996-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4056 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787468.pdf [firstpage_image] =>[orig_patent_app_number] => 665065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4006882 [patent_doc_number] => 05960456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method and apparatus for providing a readable and writable cache tag memory' [patent_app_type] => 1 [patent_app_number] => 8/649365 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3549 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960456.pdf [firstpage_image] =>[orig_patent_app_number] => 649365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3745740 [patent_doc_number] => 05694599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Data control system for a computer\'s main memory for efficiently realizing virtualization of list structure data living across a real memory space and a virtual memory space' [patent_app_type] => 1 [patent_app_number] => 8/649775 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 5301 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694599.pdf [firstpage_image] =>[orig_patent_app_number] => 649775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3671265 [patent_doc_number] => 05627993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Methods and systems for merging data during cache checking and write-back cycles for memory reads and writes' [patent_app_type] => 1 [patent_app_number] => 8/639398 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7956 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627993.pdf [firstpage_image] =>[orig_patent_app_number] => 639398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3872351 [patent_doc_number] => 05768559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Multiple bank structured memory access device having flexible setting of a pipeline stage number' [patent_app_type] => 1 [patent_app_number] => 8/635568 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 73 [patent_no_of_words] => 13422 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768559.pdf [firstpage_image] =>[orig_patent_app_number] => 635568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495297 [patent_doc_number] => 06418508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Information storage controller for controlling the reading/writing of information to and from a plurality of magnetic disks and an external device' [patent_app_type] => B1 [patent_app_number] => 08/604829 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4422 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418508.pdf [firstpage_image] =>[orig_patent_app_number] => 08604829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943097 [patent_doc_number] => 05878213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Methods, systems and computer program products for the synchronization of time coherent caching system' [patent_app_type] => 1 [patent_app_number] => 8/601753 [patent_app_country] => US [patent_app_date] => 1996-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 16913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878213.pdf [firstpage_image] =>[orig_patent_app_number] => 601753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3708782 [patent_doc_number] => 05678009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method and apparatus providing fast access to a shared resource on a computer bus' [patent_app_type] => 1 [patent_app_number] => 8/599921 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4583 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678009.pdf [firstpage_image] =>[orig_patent_app_number] => 599921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700760 [patent_doc_number] => 05696957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Integrated circuit comprising a central processing unit for executing a plurality of programs' [patent_app_type] => 1 [patent_app_number] => 8/593482 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9309 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696957.pdf [firstpage_image] =>[orig_patent_app_number] => 593482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767263 [patent_doc_number] => 05721865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory' [patent_app_type] => 1 [patent_app_number] => 8/588503 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 56 [patent_no_of_words] => 25946 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721865.pdf [firstpage_image] =>[orig_patent_app_number] => 588503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805876 [patent_doc_number] => 05737745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Redundant array of disks with host notification process for improved storage and recovery speed' [patent_app_type] => 1 [patent_app_number] => 8/582872 [patent_app_country] => US [patent_app_date] => 1996-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 10109 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737745.pdf [firstpage_image] =>[orig_patent_app_number] => 582872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3636655 [patent_doc_number] => 05603010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Performing speculative system memory reads prior to decoding device code' [patent_app_type] => 1 [patent_app_number] => 8/580323 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3734 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603010.pdf [firstpage_image] =>[orig_patent_app_number] => 580323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824943 [patent_doc_number] => 05710907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Hybrid NUMA COMA caching system and methods for selecting between the caching modes' [patent_app_type] => 1 [patent_app_number] => 8/577283 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8960 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710907.pdf [firstpage_image] =>[orig_patent_app_number] => 577283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4020364 [patent_doc_number] => 05860151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Data cache fast address calculation system and method' [patent_app_type] => 1 [patent_app_number] => 8/568609 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6234 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860151.pdf [firstpage_image] =>[orig_patent_app_number] => 568609 [rel_patent_id] =>[rel_patent_doc_number] =>)