Sheila V. Clark

Array ( [id] => 16536529 [patent_doc_number] => 10879142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Electronic component [patent_app_type] => utility [patent_app_number] => 16/407257 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5835 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14778347 [patent_doc_number] => 20190264071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR-BONDING RESIN COMPOSITION, SEMICONDUCTOR-BONDING SHEET, AND SEMICONDUCTOR DEVICE USING SEMICONDUCTOR-BONDING SHEET [patent_app_type] => utility [patent_app_number] => 16/406124 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16593865 [patent_doc_number] => 10903142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Micro through-silicon via for transistor density scaling [patent_app_type] => utility [patent_app_number] => 16/402482 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5593 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15331705 [patent_doc_number] => 20200006182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => WARPAGE CONTROL OF SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 16/402042 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16280133 [patent_doc_number] => 10763173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Thin semiconductor package and related methods [patent_app_type] => utility [patent_app_number] => 16/395822 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16789160 [patent_doc_number] => 10991599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Self-aligned via and plug patterning for back end of line (BEOL) interconnects [patent_app_type] => utility [patent_app_number] => 16/390922 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16067707 [patent_doc_number] => 10692817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Semiconductor device with shielding structure for cross-talk reduction [patent_app_type] => utility [patent_app_number] => 16/388635 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 43 [patent_no_of_words] => 11414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14722549 [patent_doc_number] => 20190252338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES INCLUDING A REDISTRIBUTION LAYER [patent_app_type] => utility [patent_app_number] => 16/387771 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14722501 [patent_doc_number] => 20190252314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => SEMICONDUCTOR PACKAGING STRUCTURE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/383003 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16383003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676557 [patent_doc_number] => 20190237393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => Integrated Circuit (IC) Package with a Solder Receiving Area and Associated Methods [patent_app_type] => utility [patent_app_number] => 16/380591 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16249411 [patent_doc_number] => 10748786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Semiconductor device with tiered pillar and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/378741 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6751 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676581 [patent_doc_number] => 20190237405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => INTEGRATED FAN-OUT PACKAGING [patent_app_type] => utility [patent_app_number] => 16/378397 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14573609 [patent_doc_number] => 20190214412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => FLEXIBLE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/355407 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16372471 [patent_doc_number] => 10804237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/353525 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3342 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15388761 [patent_doc_number] => 10535579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Power semiconductor device and package [patent_app_type] => utility [patent_app_number] => 16/298483 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14542367 [patent_doc_number] => 20190206805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => GRAPHENE-CONTAINING MATERIALS FOR COATING AND GAP FILLING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/296841 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14542337 [patent_doc_number] => 20190206790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => ELECTRONIC COMPONENT DEVICE [patent_app_type] => utility [patent_app_number] => 16/296281 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16264554 [patent_doc_number] => 10755998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Metal member, composite of metal member and resin member, and production method therefor [patent_app_type] => utility [patent_app_number] => 16/296868 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 10373 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16746473 [patent_doc_number] => 10971474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Package integration for high bandwidth memory [patent_app_type] => utility [patent_app_number] => 16/289975 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16034921 [patent_doc_number] => 10679892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-09 [patent_title] => Multi-buried ULK field in BEOL structure [patent_app_type] => utility [patent_app_number] => 16/288940 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5911 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288940 [rel_patent_id] =>[rel_patent_doc_number] =>)