Sheila V. Clark

Array ( [id] => 9303950 [patent_doc_number] => 20140042624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach' [patent_app_type] => utility [patent_app_number] => 14/061610 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4219 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13099773 [patent_doc_number] => 10069236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Waterproof structure of pad, waterproof pad, and method for forming waterproof structure [patent_app_type] => utility [patent_app_number] => 14/058419 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9305108 [patent_doc_number] => 20140043782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET' [patent_app_type] => utility [patent_app_number] => 14/058863 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9649316 [patent_doc_number] => 08803338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Semiconductor device having under-bump metallization (UBM) structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 14/057045 [patent_app_country] => US [patent_app_date] => 2013-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10093121 [patent_doc_number] => 09129951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Coated lead frame bond finger' [patent_app_type] => utility [patent_app_number] => 14/056930 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2124 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10370308 [patent_doc_number] => 20150255313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'Method for Producing a Multiplicity of Optoelectronic Semiconductor Components' [patent_app_type] => utility [patent_app_number] => 14/436578 [patent_app_country] => US [patent_app_date] => 2013-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5343 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14436578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9648492 [patent_doc_number] => 08802502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'TSOP with impedance control' [patent_app_type] => utility [patent_app_number] => 14/052037 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3911 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10047419 [patent_doc_number] => 09087825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Semiconductor structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/049253 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1802 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14049253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11645061 [patent_doc_number] => 09666451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Self-aligned via and plug patterning for back end of line (BEOL) interconnects' [patent_app_type] => utility [patent_app_number] => 14/914095 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10332 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10858221 [patent_doc_number] => 08884424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Semiconductor package with single sided substrate design and manufacturing methods thereof' [patent_app_type] => utility [patent_app_number] => 14/033673 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 61 [patent_no_of_words] => 14469 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10624467 [patent_doc_number] => 09343417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Hollow metal pillar packaging scheme' [patent_app_type] => utility [patent_app_number] => 14/030157 [patent_app_country] => US [patent_app_date] => 2013-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2147 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14030157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9223079 [patent_doc_number] => 20140017854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'CHIP PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/030058 [patent_app_country] => US [patent_app_date] => 2013-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2894 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14030058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9905673 [patent_doc_number] => 20150060872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'Encapsulated Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 14/013495 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8155 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10172065 [patent_doc_number] => 09202778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Integrated circuit package with die attach paddle having at least one recessed portion' [patent_app_type] => utility [patent_app_number] => 13/974323 [patent_app_country] => US [patent_app_date] => 2013-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2066 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13974323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10138467 [patent_doc_number] => 09171789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Lead frame, semiconductor package including the lead frame, and method of manufacturing the lead frame' [patent_app_type] => utility [patent_app_number] => 13/958980 [patent_app_country] => US [patent_app_date] => 2013-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8193 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13958980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10060078 [patent_doc_number] => 09099442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods' [patent_app_type] => utility [patent_app_number] => 13/959429 [patent_app_country] => US [patent_app_date] => 2013-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4000 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13959429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10574298 [patent_doc_number] => 09296925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Film-like adhesive, adhesive sheet for semiconductor junction, and method for producing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/418661 [patent_app_country] => US [patent_app_date] => 2013-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12165 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14418661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10486958 [patent_doc_number] => 20150371978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'POST-CMOS PROCESSING AND 3D INTEGRATION BASED ON DRY-FILM LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 14/418842 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7052 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14418842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9148419 [patent_doc_number] => 20130302942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => '3D IC CONFIGURATION WITH CONTACTLESS COMMUNICATION' [patent_app_type] => utility [patent_app_number] => 13/945169 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10309323 [patent_doc_number] => 20150194324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'PRODUCING METHOD OF ENCAPSULATING LAYER-COVERED SEMICONDUCTOR ELEMENT AND PRODUCING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/412746 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12515 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14412746 [rel_patent_id] =>[rel_patent_doc_number] =>)