Search

Sheila V. Clark

Examiner (ID: 7169, Phone: (571)272-1725 , Office: P/2896 )

Most Active Art Unit
2815
Art Unit(s)
2607, 2896, 2891, 2504, 2503, 2508, 2815, 2823
Total Applications
3274
Issued Applications
2860
Pending Applications
49
Abandoned Applications
366

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9649296 [patent_doc_number] => 08803315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'High-frequency module and communication apparatus' [patent_app_type] => utility [patent_app_number] => 13/753370 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6860 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753370 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753370
High-frequency module and communication apparatus Jan 28, 2013 Issued
Array ( [id] => 9355953 [patent_doc_number] => 08674492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Power module' [patent_app_type] => utility [patent_app_number] => 13/748422 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5224 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748422
Power module Jan 22, 2013 Issued
Array ( [id] => 9600868 [patent_doc_number] => 20140197551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'Method for Fabricating a Semiconductor Chip Panel' [patent_app_type] => utility [patent_app_number] => 13/741113 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741113 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741113
Method for fabricating a semiconductor chip panel Jan 13, 2013 Issued
Array ( [id] => 9274037 [patent_doc_number] => 08637971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/738578 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4338 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/738578
Semiconductor device and method of manufacturing semiconductor device Jan 9, 2013 Issued
Array ( [id] => 9406282 [patent_doc_number] => 20140097534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'DUAL-PHASE INTERMETALLIC INTERCONNECTION STRUCTURE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/736088 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4177 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736088
Dual-phase intermetallic interconnection structure and method of fabricating the same Jan 7, 2013 Issued
Array ( [id] => 9432924 [patent_doc_number] => 20140110830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/735667 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4865 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735667
Semiconductor package Jan 6, 2013 Issued
Array ( [id] => 11201143 [patent_doc_number] => 09431364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Multi-chip package assembly with improved bond wire separation' [patent_app_type] => utility [patent_app_number] => 13/735650 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4783 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735650
Multi-chip package assembly with improved bond wire separation Jan 6, 2013 Issued
Array ( [id] => 8821608 [patent_doc_number] => 20130122653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Stacked Package And Method Of Manufacturing The Same' [patent_app_type] => utility [patent_app_number] => 13/735391 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735391
Stacked Package And Method Of Manufacturing The Same Jan 6, 2013 Abandoned
Array ( [id] => 9594701 [patent_doc_number] => 20140191378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/734246 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734246 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734246
Integrated circuit package Jan 3, 2013 Issued
Array ( [id] => 9965411 [patent_doc_number] => 09013028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Integrated circuit package and method of making' [patent_app_type] => utility [patent_app_number] => 13/734402 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3159 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734402 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734402
Integrated circuit package and method of making Jan 3, 2013 Issued
Array ( [id] => 9557969 [patent_doc_number] => 20140175681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH' [patent_app_type] => utility [patent_app_number] => 13/722603 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722603
Absorbing excess under-fill flow with a solder trench Dec 19, 2012 Issued
Array ( [id] => 9557915 [patent_doc_number] => 20140175627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'LEAD FRAME HAVING A PERIMETER RECESS WITHIN PERIPHERY OF COMPONENT TERMINAL' [patent_app_type] => utility [patent_app_number] => 13/722063 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722063 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722063
Lead frame having a perimeter recess within periphery of component terminal Dec 19, 2012 Issued
Array ( [id] => 10022476 [patent_doc_number] => 09064971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Methods of forming ultra thin package structures including low temperature solder and structures formed therby' [patent_app_type] => utility [patent_app_number] => 13/721329 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3467 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721329
Methods of forming ultra thin package structures including low temperature solder and structures formed therby Dec 19, 2012 Issued
Array ( [id] => 8887902 [patent_doc_number] => 20130161087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'SOLDER BALL DEVICE, HOUSING HAVING A SOLDER BALL DEVICE AND PRODUCTION PROCESS FOR A SOLDER BALL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/720264 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1670 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720264 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/720264
SOLDER BALL DEVICE, HOUSING HAVING A SOLDER BALL DEVICE AND PRODUCTION PROCESS FOR A SOLDER BALL DEVICE Dec 18, 2012 Abandoned
Array ( [id] => 10151841 [patent_doc_number] => 09184138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Semiconductor integrated device with mechanically decoupled active area and related manufacturing process' [patent_app_type] => utility [patent_app_number] => 13/719103 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5289 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719103
Semiconductor integrated device with mechanically decoupled active area and related manufacturing process Dec 17, 2012 Issued
Array ( [id] => 9118300 [patent_doc_number] => 20130285222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/716652 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3719 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716652 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716652
Semiconductor package and method of manufacturing the same Dec 16, 2012 Issued
Array ( [id] => 10838605 [patent_doc_number] => 08866286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Single layer coreless substrate' [patent_app_type] => utility [patent_app_number] => 13/713550 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6364 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13713550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/713550
Single layer coreless substrate Dec 12, 2012 Issued
Array ( [id] => 9534587 [patent_doc_number] => 20140159233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/708461 [patent_app_country] => US [patent_app_date] => 2012-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13708461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/708461
Package on package structure and method of manufacturing the same Dec 6, 2012 Issued
Array ( [id] => 9534582 [patent_doc_number] => 20140159228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/707159 [patent_app_country] => US [patent_app_date] => 2012-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5101 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13707159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/707159
High density substrate routing in BBUL package Dec 5, 2012 Issued
Array ( [id] => 8863345 [patent_doc_number] => 20130147048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'INTEGRATED CIRCUIT DEVICES INCLUDING ELECTRODE SUPPORT STRUCTURES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/707394 [patent_app_country] => US [patent_app_date] => 2012-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13707394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/707394
Integrated circuit devices including electrode support structures and methods of fabricating the same Dec 5, 2012 Issued
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